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Volumn 21, Issue 2, 2010, Pages 191-210

Analog/mixed-signal circuit verification using models generated from simulation traces

Author keywords

Abstract model generation; Analog mixed signal circuits; Formal methods; Hybrid Petri nets

Indexed keywords


EID: 77951671571     PISSN: 01290541     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0129054110007209     Document Type: Article
Times cited : (16)

References (20)
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  • 4
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  • 6
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    • (2006) Formal Modelling and Analysis of Timed Systems , vol.4202 , pp. 171-186
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  • 8
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  • 9
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  • 10
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    • Verification of analog/mixed-signal circuits using labeled hybrid petri nets
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    • Analog/mixed-signal circuit verification using models generated from simulation traces
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    • S. Little, D. Walter, and C. Myers. Analog/mixed-signal circuit verification using models generated from simulation traces. In K. S. Namjoshi, T. Yoneda, T. Higashino, and Y. Okamura, editors, Automated Technology for Verification and Analysis, volume 4762 of LNCS, pages 114-128. Springer, 2007.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.