Combining symbolic simulation and interval arithmetic for the verification of AMS designs

Proceedings - Formal Methods in Computer Aided Design, FMCAD 2007

Volumn , Issue , 2007, Pages 207-215

  Zaki, Mohamed H ^a   Al Sammane, Ghiath ^a   Tahar, Sofiène ^a   Bois, Guy ^b  

^a Dept of Electrical and Computer Engineering   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALPHA PARTICLE SPECTROMETERS; ANALOG CIRCUITS; APPROXIMATION ALGORITHMS; ASSET MANAGEMENT; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DIFFERENCE EQUATIONS; DIGITAL ARITHMETIC; EQUATIONS OF STATE; FORMAL METHODS; INTEGRATED CIRCUITS; PARTICLE SPECTROMETERS; SPACE RESEARCH; STATE SPACE METHODS;

ANALOG AND MIXED SIGNAL (AMS); BOUNDED MODEL CHECKING (BMC); COMBINED SYSTEMS; DIGITAL PARTS; ELECTRONIC SYSTEMS; FORMAL TECHNIQUES; INTERVAL ARITHMETIC (IA); OSCILLATOR CIRCUITS; REAL WORLD; STATE SPACES; SYMBOLIC SIMULATION; TAYLOR APPROXIMATIONS;

MODEL CHECKING;

EID: 47349131037     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FAMCAD.2007.25     Document Type: Conference Paper

References (24)

1. G. Al-Sammane. Simulation Symbolique des Circuits Decrits au Niveau Algorithmique. PhD thesis, Université Joseph Fourier, Grenoble, France, July 2005.
2. G. Al Sammane, M. Zaki, and S. Tahar. A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs. IEEE/ACM Design Automation and Test in Europe, pp. 249-254, 2007.
3. M. Berz, G. Hoffsttter. Computation and Application of Taylor Polynomials with Interval Remainder Bounds, Reliable Computing, 4(1): 83-97, Springer, 1998.
4. E.M. Clarke, O. Grumberg, and D.A. Peled. Model Checking. MIT Press, 2000.
5. E. M. Clarke, D. Kroening, J. Ouaknine, and O. Strichman. Computational challenges in bounded model checking. International Journal on Software Tools for Technology Transfer, 7(2): 174-183, Springer, 2005.
6. T. Dang, A. Donze, O. Maler. Verification of Analog and Mixedsignal Circuits using Hybrid System Techniques. In Formal Methods in Computer-Aided Design, LNCS 3312, pp. 14-17, Springer, 2004.
7. M. Freibothe, J. Schoenherr, and B. Straube. Formal Verification of the Quasi-Static Behavior of Mixed-Signal Circuits by Property Checking, Electr. Notes Theor. Comput. Sci., 153(3):23-35, Elsevier, 2006.
8. G. Frehse, B.H. Krogh, R.A. Rutenbar. Verifying Analog Oscillator Circuits Using Forward/Backward Abstraction Refinement. IEEE/ACM Design Automation and Test in Europe, pp. 257-262, 2006.
9. S. Gupta, B.H. Krogh, R.A. Rutenbar. Towards Formal Verification of Analog Designs, IEEE/ACM International Conference on Computer Aided Design, pp. 210-217, 2004.
10. P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer. Analysis and Design of Analog Integrated Circuits, Wiley, 2001
11. M. R. Greenstreet, I. Mitchell. Reachability Analysis Using Polygonal Projections. In Hybrid Systems: Computation and Control, LNCS 1569, pp. 103-116, Springer, 1999.
12. K. Hanna. Automatic Verification of Mixed-Level Logic Circuits. In Formal Methods in Computer-Aided Design, LNCS 1522, pp.133-166, Springer, 1998.
13. W. Hartong, R. Klausen, and L. Hedrich. Formal Verification for Nonlinear Analog Systems: Approaches to Model and Equivalence Checking, Advanced Formal Verification, pp. 205-245, Kluwer, 2004.
14. T.A. Henzinger, P.-H. Ho, and H. Wong-Toi. HyTech: A Model Checker for Hybrid Systems. Software Tools for Technology Transfer, 1(1-2):110-122, Kluwer, 1997.
15. R.P. Kurshan and K.L. McMillan. Analysis of Digital Circuits Through Symbolic Reduction. IEEE Trans. on Computer-Aided Design, 10(11): 1356-71, 1991.
16. S. Little, N. Seegmiller, D. Walter, C. Myers, and T. Yoneda. Verification of Analog/mixed-signal Circuits using Labeled Hybrid Petri Nets, IEEE/ACM International Conference on Computer Aided Design , pp. 275-282, 2006.
17. S. Little, D. Walter, N. Seegmiller, C. Myers, and T. Yoneda. Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. In Automated Technology for Verification and Analysis, LNCS 3299, pp. 426-440, Springer, 2004.
18. K. Makino, M. Berz. Remainder Differential Algebras and their Applications. In Computational Differentiation: Techniques, Applications, and Tools, pp. 63-75, SIAM, 1996.
19. C. J. Myers, R. R. Harrison, D. Walter, N. Seegmiller, S. Little. The Case for Analog Circuit Verification. Electr. Notes Theor. Comput. Sci., Elsevier, 153(3):53-63, 2006.
20. R.E. Moore. Methods and Applications of Interval Analysis, Society for Industrial and Applied Mathematics, 1979.
21. S. Wolfram. Mathematica: A System for Doing Mathematics by Computer. Addison Wesley Longman Publishing, USA, 1991.
22. M. Zaki, G. Al Sammane, S. Tahar, and G. Bois. A Bounded Model Checking Approach for AMS Designs. Technical Report, ECE Dept., Concordia University, Montreal, Quebec, Canada, May 2007. http://hvg.ece.concordia.ca/Publications/ TECH_REP/AMS_BMC_TR07
23. M. Zaki, G. Al Sammane and S. Tahar. Formal Verification of Analog and Mixed Signal Designs in Mathematica, Proc. International Conference on Computational Science, LNCS 4488, pp. 263-267, Springer, 2007.
24. M. Zaki, S. Tahar, and G. Bois. Formal Verification of Analog and Mixed Signal Designs: Survey and Comparison, IEEE Northeast Workshop on Circuits and Systems, pp. 281-284, 2006.