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Volumn 1, Issue , 2006, Pages

Verifying analog oscillator circuits using forward/backward abstraction refinement

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; ITERATIVE METHODS; MATHEMATICAL MODELS; STORAGE ALLOCATION (COMPUTER); VARIABLE FREQUENCY OSCILLATORS;

EID: 34047119262     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244113     Document Type: Conference Paper
Times cited : (64)

References (11)
  • 2
    • 84958767760 scopus 로고    scopus 로고
    • Possibly not closed convex polyhedra and the Parma Polyhedra Library
    • M. V. Hermenegildo and G. Puebla, editors, Static Analysis: Proc. Int. Symp, of, Springer
    • R. Bagnara, E. Ricci, E. Zaffanella, and P. M. Hill. Possibly not closed convex polyhedra and the Parma Polyhedra Library. In M. V. Hermenegildo and G. Puebla, editors, Static Analysis: Proc. Int. Symp., volume 2477 of LNCS, pages 213-229. Springer, 2002.
    • (2002) LNCS , vol.2477 , pp. 213-229
    • Bagnara, R.1    Ricci, E.2    Zaffanella, E.3    Hill, P.M.4
  • 3
    • 46149112096 scopus 로고    scopus 로고
    • Verification of analog and mixed-signal circuits using hybrid system techniques
    • Austin, Texas
    • T. Dang, A. Donze, and O. Maler. Verification of analog and mixed-signal circuits using hybrid system techniques. In FMCAD 2004, Austin, Texas, 2004.
    • (2004) FMCAD 2004
    • Dang, T.1    Donze, A.2    Maler, O.3
  • 6
    • 34047173321 scopus 로고    scopus 로고
    • G. Frehse. PHAVer: Algorithmic verification of hybrid systems past HyTech. In M. Morari and L. Thiele, editors, Hybrid Systems: Computation and Control (HSCC'05), Mar. 9 11, 2005, Zürich, CH, 2005. PHAVer is available at http://www.es.ru.nl/~goranf/.
    • G. Frehse. PHAVer: Algorithmic verification of hybrid systems past HyTech. In M. Morari and L. Thiele, editors, Hybrid Systems: Computation and Control (HSCC'05), Mar. 9 11, 2005, Zürich, CH, 2005. PHAVer is available at http://www.es.ru.nl/~goranf/.
  • 8
    • 85057633243 scopus 로고    scopus 로고
    • Time constrained verification of analog circuits using model-checking algorithms
    • Edinburgh, Scotland, April
    • D. Grabowski, D. Platte, L. Hedrich, and E. Barke. Time constrained verification of analog circuits using model-checking algorithms. In Formal verification of Analog Circuits, Edinburgh, Scotland, April 2005.
    • (2005) Formal verification of Analog Circuits
    • Grabowski, D.1    Platte, D.2    Hedrich, L.3    Barke, E.4
  • 9
    • 16244374916 scopus 로고    scopus 로고
    • Towards formal verification of analog designs
    • Sen Jose, CA USA
    • S. Gupta, B. H. Krogh, and R. A. Rutenbar. Towards formal verification of analog designs. In ICCAD 2004, Sen Jose, CA (USA), 2004.
    • (2004) ICCAD 2004
    • Gupta, S.1    Krogh, B.H.2    Rutenbar, R.A.3
  • 10
    • 84937570416 scopus 로고    scopus 로고
    • W. Hartong, L. Hedrich, and E. Barke. On discrete modeling and model checking for nonlinear analog systems. In E. Brinksma and K. G. Larsen, editors, CAV, 2404 of LNCS, pages 401-413. Springer, 2002.
    • W. Hartong, L. Hedrich, and E. Barke. On discrete modeling and model checking for nonlinear analog systems. In E. Brinksma and K. G. Larsen, editors, CAV, volume 2404 of LNCS, pages 401-413. Springer, 2002.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.