First steps towards SAT-based formal analog verification

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 1-8

  Tiwary, Saurabh K ^a   Gupta, Anubhav ^a,b   Phillips, Joel R ^a   Pinello, Claudio ^a,c   Zlatanovici, Radu ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

^c UNITED TECHNOLOGIES RESEARCH CENTER   (United States)

Author keywords

Analog; Circuit; SPICE; Verification

Indexed keywords

COMPUTATIONAL EFFICIENCY; COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; FORMAL LOGIC; MATHEMATICAL TRANSFORMATIONS; NETWORKS (CIRCUITS); VERIFICATION;

ABSTRACTION REFINEMENT; ANALOG; ANALOG VERIFICATION; BOOLEAN SATISFIABILITY; NONLINEAR BEHAVIOR; NOVEL METHODOLOGY; PERIODIC STEADY STATE (PSS); SATISFIABILITY PROBLEMS;

SPICE;

EID: 76349119446     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687401     Document Type: Conference Paper

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