Verification of analog and mixed signal designs using online monitoring

2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop, IMS3TW '09

Volumn , Issue , 2009, Pages

  Wang, Zhiwei ^a   Abbasi, Naeem ^a   Narayanan, Rajeev ^a   Zaki, Mohamed H ^b   Al Sammane, Ghiath ^a   Tahar, Sofiène ^a  

^a Dept of Electrical and Computer Engineering   (Canada)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG AND MIXED SIGNALS; ANALOG AND MIXED-SIGNAL DESIGN; C LANGUAGE; COMPLEX BEHAVIOR; JITTER NOISE; OFF-LINE APPROACHES; ONLINE MONITORING; ONLINE MONITORING TECHNIQUE; RUN-TIME VERIFICATION; RUNTIMES; SPECIFICATION AND VERIFICATION; STATE SPACE; SYSTEM OF RECURRENCE EQUATIONS; SYSTEM ON CHIP DESIGN; VERIFICATION TECHNIQUES; VOLTAGE CONTROLLED OSCILLATOR;

ANALOG CIRCUITS; JITTER; PARTIAL DISCHARGES; SENSORS;

DESIGN;

EID: 70350379038     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMS3TW.2009.5158695     Document Type: Conference Paper

References (17)

1. N. Abbasi, R. Narayanan, G. Al Sammane, M.H. Zaki, and S. Tahar. Enabling AMS Simulation using Recurrence Notations, Technical Report, Department of ECE, Concordia University, Montreal, QC, Canada. May 2008. http://hvg.ece.concordia. ca/Publications/TECH-REP/CSRE-TR08
2. Accellera PSL. http://www.accellera.org/
3. R. E. Best. Phase-Locked Loops: Design, Simulation, and Applications. McGraw-Hill, 2003.
4. C. Eisner. PSL for Runtime Verification: Theory and Practice. Runtime Verification, LNCS 4839, pp. 1-8, Springer, 2007.
5. E.A. Emerson. Temporal and Modal Logic. Handbook of Theoretical Computer Science, pages 995-1072. Elsevier, 1990.
6. G. Frehse, B.H. Krogh, and R.A. Rutenbar. Time Domain Verification of Oscillator Circuit Properties. Workshop on Formal Verification of Analog Circuits, ENTCS, 153(3): 9-22, 2006.
7. A. Jesser, S. Laemmermann, A. Pacholik, R. Weiss, J. Ruf, L. Hedrich, W. Fengler, T. Kropf, and W. Rosenstiel. Advanced Assertion Based Design for Mixed-Signal Verification. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E91(A12):3548-3555, 2008.
8. K. Kundert, H. Chang, D. Jefferies, G. Lamant, E. Malavasi, and F. Sendig. Design of Mixed-Signal Systems-on-a-Chip. IEEE Trans. on CAD, 19(12): 1561-1571, 2000.
9. K. Kundert. Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers. http://www.designers-guide.org/Analysis/PLLnoise +jitter.pdf
10. O. Maler, and D. Nickovic. Monitoring Temporal Properties of Continuous Signals. Formal Modelling and Analysis of Timed Systems, LNCS 3253, pp. 152-166, Springer, 2004.
11. O. Maler, D. Nickovic, and A. Pnueli. Checking Temporal Properties of Discrete, Timed and Continuous Behavior. Pillars of Computer Science, LNCS 4800, pp. 475-505, Springer, 2008.
12. MLDesign Tech., Inc. http://www.mldesigner.com
13. K. Morin-Allory, L. Fesquet, B. Roustan, and D. Borrione. Asynchronous Online Monitoring of Logical and Temporal Assertions. Embedded Systems Specification and Design Languages, LNEE 10, pp. 243-253, Springer, 2008.
14. D. Nickovic, and O. Maler. AMT: A Property-Based Monitoring Tool for Analog System. Formal Modelling and Analysis of Timed Systems, LNCS 4763, pp. 304-319, Springer, 2007
15. B. Razavi. RF Microelectronics, Prentice Hall, 1997.
16. G. Al Sammane, M.H. Zaki, Z.J. Dong, and S. Tahar. Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL. Forum on Specification & Design Languages, pp. 293-298, 2007.
17. M. Zaki, S. Tahar and G. Bois. Formal Verification of Analog and Mixed Signal Designs: A Survey. Microelectronics Journal, 39(12):1395-1404, Elsevier, 2008.