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Volumn , Issue , 2004, Pages 210-217

Towards formal verification of analog designs

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUIT VERIFICATIONS; CIRCUIT BEHAVIORS; FINITE-STATE ABSTRACTIONS; HYBRID SYSTEM MODEL CHECKING;

EID: 16244374916     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2004.1382573     Document Type: Conference Paper
Times cited : (81)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.