A Tri-modal 20-Gbps/link differential/DDR3/GDDR5 memory interface

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 4, 2012, Pages 926-937

  Kaviani, Kambiz ^a   Wu, Ting ^b   Wei, Jason ^a   Amirkhany, Amir ^a   Shen, Jie ^a   Chin, T J ^a   Thakkar, Chintan ^c   Beyene, Wendemagegnehu T ^a   Chan, Norman ^a   Chen, Catherine ^a   Chuang, Bing Ren ^a   Dressler, Deborah ^a   Gadde, Vijay P ^a   Hekmat, Mohammad ^a   Ho, Eugene ^a   Huang, Charlie ^a   Le, Phuong ^a   Mahabaleshwara, ^d   Madden, Chris ^a   Mishra, Navin Kumar ^d   Raghavan, Lenesh ^e   Saito, Keisuke ^a   Schmitt, Ralf ^a   Secker, Dave ^a   Shi, Xudong ^a   Fazeel, Shuaeb ^f   Srinivas, Gundlapalli Shanmukha ^d   Zhang, Steve ^a   Tran, Chanh ^a   Vaidyanath, Arun ^a   Vyas, Kapil ^d   Jain, Manish ^d   Chang, Kun Yung Ken ^g   Yuan, Xingchao ^a   more..

^a RAMBUS INC   (United States)

^b Norel Systems   (China)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d Rambus India Design Center   (India)

^e INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^f TEXAS INSTRUMENTS   (India)

^g XILINX INC   (United States)

Author keywords

Calibration; clocking; DDR; decision feedback equalization; GDDR; high voltage protection; multi standard memory interface; multi VCO PLL; offset cancellation; predictive DFE; quadrature generator

Indexed keywords

CLOCKING; DDR; DECISION-FEEDBACK EQUALIZATIONS; GDDR; HIGH-VOLTAGES; MEMORY INTERFACE; OFFSET CANCELLATION; QUADRATURE GENERATOR;

CALIBRATION; CLOCKS; CMOS INTEGRATED CIRCUITS; VLSI CIRCUITS;

ELECTRIC EQUIPMENT PROTECTION;

EID: 84862797743     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2185370     Document Type: Conference Paper

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