Replica compensated linear regulators for supply-regulated phase-locked loops

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 2, 2006, Pages 413-424

  Alon, Elad ^a,b,c,f   Kim, Jaeha ^a,d   Pamarti, Sudhakar ^a,e   Chang, Ken ^a,c   Horowitz, Mark ^a,b,c,g  

^a IEEE   (United States)

^b Stanford University   (United States)

^c RAMBUS INC   (United States)

^d Seoul National University   (South Korea)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f HEWLETT PACKARD COMPANY   (United States)

^g STANFORD UNIVERSITY   (United States)

Author keywords

Phase locked loops; Power supply noise; Regulators

Indexed keywords

PHASE-LOCKED LOOPS; POWER SUPPLY NOISE; REGULATORS; SUPPLY REJECTION LIMITING COMPONENTS;

ACOUSTIC NOISE; COMPUTER SIMULATION; ELECTRIC CURRENT REGULATORS; JITTER; LINEAR CONTROL SYSTEMS; PHASE LOCKED LOOPS; POWER CONTROL; VOLTAGE CONTROL;

POWER SUPPLY CIRCUITS;

EID: 31644441207     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.862347     Document Type: Article

References (12)

1. V. von Kaenel et al, "A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1715-1722, Nov. 1996.
2. S. Sidiropoulos et al., "Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers," in Symp. VLSI Circuits Dig. Tech, Papers, Jun. 2000, pp. 124-127.
3. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw Hill, 2000.
4. J. Kim, "Design of CMOS adaptive-supply serial links," Ph.D. dissertation, Stanford Univ., Stanford, CA, Dec. 2002.
5. M.-J. E. Lee et al., "Low-power area-efficient high-speed I/O circuit techniques," IEEE J. Solid-State Ciruits, vol. 35, no. 11, pp. 1591-1599, Nov. 2000.
6. K.-Y. K. Chang et al., "A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 747-754, May 2003.
7. K. Chang et al., "Clocking and circuit design for a parallel I/O on a first-generation CELL processor," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, p. 526.
8. G. W. den Besten and B. Nauta, "Embedded 5-V-to-3.3-V voltage regulator for supplying digital ICs in 3.3 V technology," IEEE J. Solid-State Ciruits, vol. 33, no. 7, pp. 956-962, Jul. 1998.
9. J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
10. A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
11. E. Alon, V. Stojanović, and M. A. Horowitz, "Circuits and techniques for high-resolution measurement of on-chip power supply noise," IEEE J. Solid-State Ciruits, vol. 40, no. 4, pp. 820-828, Apr. 2005.
12. M. Mansuri and C.-K. K. Yang, "Jitter optimization based on phase-locked loop design parameters," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1375-1382, Nov. 2002.