A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 498-499

  Bae, Seung Jun ^a   Sohn, Young Soo ^a   Oh, Tae Young ^a   Kim, Si Hong ^a   Yang, Yun Seok ^a   Kim, Dae Hyun ^a   Kwak, Sang Hyup ^a   Seol, Ho Seok ^a   Shin, Chang Ho ^a   Park, Min Sang ^a   Han, Gong Heom ^a   Kim, Byeong Cheol ^a   Cho, Yong Ki ^a   Kim, Hye Ran ^a   Doo, Su Yeon ^a   Kim, Young Sik ^a   Kang, Dong Seok ^a   Choi, Young Ryeol ^a   Bang, Sam Young ^a   Park, Sun Young ^a   Shin, Yong Jae ^a   Moon, Gil Shin ^a   Park, Cheol Goo ^a   Kim, Woo Seop ^a   Yang, Hyang Ja ^a   Lim, Jeong Don ^a   Park, Kwang Il ^a   Choi, Joo Sun ^a   Jun, Young Hyun ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; EQUALIZERS; MICROSTRIP LINES; OSCILLISTORS; PHASE LOCKED LOOPS; POLYCHLORINATED BIPHENYLS; SHIELDING;

BACKWARD COMPATIBILITY; CHANNEL CROSSTALK; CHANNEL EQUALIZATION; ERROR DETECTION CODING; INJECTION LOCKED OSCILLATORS; NUMBER OF LAYERS; POWER INTEGRITY; SPEED IMPROVEMENT;

CROSSTALK;

EID: 79955742428     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746414     Document Type: Conference Paper

References (6)

1. Seung-Jun Bae, Young-Soo Sohn, Kwang-II Park, et al, "A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques," ISSCC Dig. Tech. Papers, pp.278-613, Feb. 2008.
2. Kho, R., Boursin, D., Brox, M, et al, "75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques," ISSCC Dig. Tech. Papers, pp.134-135, Feb. 2009.
3. Seung-Jun Bae, Young-Soo Sohn, Tae-young Oh, et al, "A 40nm 7Gb/s/pin Single-ended Transceiver with Jitter and ISI Reduction Techniques for High-Speed DRAM Interface," Symp. VLSI Circuits, Dig. Tech. Papers, pp.193-194, Jun. 2010.
4. Zerbe, J.L., Chau, P.S., et al, "A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers," ISSCC Dig. Tech. Papers, pp.66-67, Feb. 2001
5. Sham, K., Ahmadi, M., et al, "FEXT Crosstalk Cancellation for High-Speed Serial Link Design," IEEE CICC, pp. 405-406, Sept. 2006.
6. F. O'Mahony, S. Shekhar, M. Mansuri, et al., "A 27 Gb/s forwarded-clock I/O receiver using an injection-locked LC-DCO in 45nm CMOS," ISSCC Dig. Tech. Papers, pp. 452-453, Feb. 2008.