A CMOS multi-channel 10Gb/s transceiver

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Takauchi, Hideki ^a   Tamura, Hirotaka ^a   Matsubara, Satoshi ^a   Kibune, Masaya ^a   Doi, Yoshiyasu ^a   Chiba, Takaya ^a   Anbutsu, Hideaki ^a   Yamaguchi, Hisakatsu ^a   Mori, Toshihiko ^a   Takatsu, Motomu ^a   Gotoh, Kohtaroh ^a   Sakai, Toshiaki ^a   Yamamura, Takashi ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; MODULATION; PHASE LOCKED LOOPS; TIMING CIRCUITS; TRANSMITTERS;

CLOCK RECOVERY UNIT; DECISION CIRCUIT; DIGITAL LOOP FILTER; FRONT END SAMPLER; PHASE INTERPOLATOR; SERIAL-TO-PARALLEL CONVERTER;

TRANSCEIVERS;

EID: 0038306652     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. S. Sidiropoulos, et al., "A Semidigital Dual Delay-Locked Loop," IEEE Journal of Solid-State Circuits, vol. 32, no. 11, November 1997, pp. 1083-1092.