A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 372-373

  Balamurugan, Ganesh ^a   O'Mahony, Frank ^a   Mansuri, Mozhgan ^a   Jaussi, James E ^a   Kennedy, Joseph T ^a   Casper, Bryan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BACKPLANES; HIGH-SPEED DIGITAL SYSTEMS; INTERCHIP COMMUNICATIONS; MULTI-LEVEL SIGNALING; OPTIMAL POWER; PERFORMANCE SCALABILITY; RE-CONFIGURABLE; SERVER SYSTEM; SINGLE-ENDED; TRANSCEIVER DESIGN;

MICROPROCESSOR CHIPS; TRANSCEIVERS;

SIGNALING;

EID: 77952124330     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433826     Document Type: Conference Paper

References (6)

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2. V. Stojanovic, et al., "Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery," IEEE J. Solid-State Circuits,vol. 40, no. 4, pp. 1012-1026, April, 2005.
3. G. Balamurugan, et al., "A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS," IEEE J. Solid-State Circuits, vol.43, no. 4, pp.1010-1019, April, 2008.
4. C. Menolfi, et al., "A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI," ISSCC Dig. Tech. Papers, pp.446-614, Feb., 2007.
5. K. Krishna, et al., "A Multi-Gigabit Backplane Transceiver Core in 0.13-μm CMOS with a Power-Efficient Equalization Architecture," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2658-2666, Dec., 2005.
6. B. Casper, et al., "An 8-Gb/s Simultaneous Bidirectional Link With On-Die Waveform Capture," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2111-2120, Dec., 2003.