Modeling cache contention and throughput of multiprogrammed manycore processors

IEEE Transactions on Computers

Volumn 61, Issue 7, 2012, Pages 913-927

  Chen, Xi E ^a   Aamodt, Tor ^b  

^a NVIDIA   (United States)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

Analytical modeling; cache contention; fine grained multithreading; manycore; throughput

Indexed keywords

ACCESS LOCALITY; ANALYTICAL MODELING; ASSOCIATIVITY; AVERAGE ERRORS; CACHE CONTENTION; CACHE MISS RATES; CIRCULAR SEQUENCES; COMBINED MODEL; CONCURRENT THREADS; MANY-CORE; MANY-CORE ARCHITECTURE; MARKOV CHAIN MODELS; MEMORY ACCESS; MISS-RATE; MULTI-THREADING; MULTITHREADED; OPTIMIZED DESIGNS; SHARED CACHE; THROUGHPUT MODELS;

ANALYTICAL MODELS; MARKOV PROCESSES; MICROPROCESSOR CHIPS; MULTITASKING;

THROUGHPUT;

EID: 84861811396     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2011.141     Document Type: Review

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