A first-order fine-grained multithreaded throughput model

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 329-340

  Chen, Xi E ^a   Aamodt, Tor M ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; FORECASTING; MARKOV CHAINS;

APPLICATION SPECIFIC; CHIP MULTIPROCESSOR; MULTITHREADED ARCHITECTURE; PERFORMANCE SIMULATION; PERFORMANCE SIMULATOR; PROBABILISTIC MODELING; THROUGHPUT MODELING; TRANSITION PROBABILITIES;

ANALYTICAL MODELS;

EID: 64949101685     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798270     Document Type: Conference Paper

References (28)

1. V. S. Adve and M. K. Vernon. Parallel Program Performance Prediction Using Deterministic Task Graph Analysis. ACM TOCS, 22(1):94-136, 2004.
2. A. Agarwal, M. Horowitz, and J. Hennessy. An Analytical Cache Model. ACM TOCS, 7(2):184-215, 1989.
3. D. Chandra, F. Guo, S. Kim, and Y. Solihin. Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture. In HPCA-11, pages 340-351, 2005.
4. X. E. Chen and T. M. Aamodt. Hybrid Analytical Modeling of Pending Cache Hits, Data Prefetching, and MSHRs. In MICRO-41, pages 59-70, 2008.
5. D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. H. Reinhart, D. E. Johnson, J. Keefe, and H. Angepat. FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. In MICRO-40, pages 249-261, 2007.
6. B. Cmelik and D. Keppel. Shade: A Fast Instruction-set Simulator for Execution Profiling. In SIGMETRICS, pages 128-137, 1994.
7. B. Falsafi and D. A.Wood. Modeling Cost/Performance of A Parallel Computer Simulator. ACM TOMACS, 7(1):104-130, 1997.
8. V. Govindaraju, P. Djeu, K. Sankaralingam, M. Vernon, and W. R. Mark. Toward A Multicore Architecture for Real-time Ray-tracing. In MICRO-41, pages 176-187, 2008.
9. J. L. Hennessy andD. A. Patterson. Computer Architecture: A Quantitative Approach, 4th ed. Morgan Kaufmann, 2007.
10. P. G. Hoel, C. J. Stone, and S. C. Port. Introduction to Stochastic Processes. Waveland Press, 1987.
11. T. S. Karkhanis and J. E. Smith. A First-order Superscalar Processor Model. In ISCA-31, pages 338-349, 2004.
12. T. S. Karkhanis and J. E. Smith. Automated Design of Application Specific Superscalar Processors: An Analytical Approach. In ISCA-34, pages 402-411, 2007.
13. P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-Way Multithreaded Sparc Processor. IEEE Micro, 25(2):21-29, 2005.
14. P. Michaud, A. Seznec, and S. Jourdan. An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors. IJPP, 29(1):35-38, 2001.
15. TMT2 Core Microarchitecture Specification. Sun Microsystems, Inc., 2007.
16. D. B. Noonburg and J. P. Shen. Theoretical Modeling of Superscalar Processor Performance. In MICRO-27, pages 52-62, 1994.
17. D. B. Noonburg and J. P. Shen. A Framework for Statistical Modeling of Superscalar Processor Performance. In HPCA-3, 1997.
18. D. J. Ofelt. Efficient Performance Prediction for Modern Microprocessors. PhD thesis, Stanford University, 1999.
19. S. K. Reinhardt, M. D. Hill, J. R. Larus, A. R. Lebeck, J. C. Lewis, and D. A. Wood. The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers. In SIGMETRICS, pages 48-60, 1993.
20. D. Sheahan. Developing and Tuning Applications on UltraSPARC®T1 Chip Multithreading Systems. Sun Microsystems, Inc., 1.2 edition, October 2007.
21. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically Characterizing Large Scale Program Behavior. In ASPLOS-X, pages 45-57, 2002.
22. Standard Performance Evaluation Corporation. SPEC CPU2000 Benchmarks. http://www.spec.org.
23. D. Thiebaut and H. S. Stone. Footprints in the Cache. ACM TOCS, 5(4):305-329, 1987.
24. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous Multithreading: Maximizing On-Chip Parallelism. In ISCA-22, pages 392-403, 1995.
25. J. Wawrzynek, D. Patterson, M. Oskin, S.-L. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, and K. Asanovi. RAMP: Research Accelerator for Multiple Processors. IEEE Micro, 27(2):46-57, 2007.
26. W. Yamamoto, M. Serrano, A. Talcott, R. Wood, and M. Nemirosky. Performance Estimation of Multistreamed, Superscalar Processors. In 27th Hawaii Int'l Conf. System Sciences, Jan. 1994.
27. J. J. Yi, L. Eeckhout, D. J. Lilja, B. Calder, L. K. John, and J. E. Smith. The Future of Simulation: A Field of Dreams. Computer, 39(11):22-29, 2006.
28. L. Zhao, R. R. Iyer, J. Moses, R. Illikkal, S. Makineni, and D. Newell. Exploring Large-Scale CMP Architectures Using ManySim. IEEE Micro, 27(4):21-33, 2007.