A read-monitored write circuit for 1T1M multi-level memristor memories

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 2938-2941

  Manem, Harika ^a   Rose, Garrett S ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA CELLS; HYBRID CMOS; LOGIC SYSTEMS; LOW-POWER CONSUMPTION; MEMRISTOR; MOLECULAR SCALE; MULTI-LEVEL; NANO SCALE; PROPOSED ARCHITECTURES; READ NOISE; TECHNOLOGY MIGRATION; WRITE SPEED;

ARCHITECTURE; LOW POWER ELECTRONICS; MEMORY ARCHITECTURE; MEMRISTORS; PASSIVE FILTERS; RESISTORS;

LOGIC CIRCUITS;

EID: 79960858494     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5938207     Document Type: Conference Paper

References (12)

1. S. Kim, Y. Zhang, B. Lee; M. Caldwell, H. -S. P. Wong, "Fabrication and characterization of emerging nanoscale memory," ISCAS, pp. 65-68, 2009.
2. M. M. Ziegler and M. R. Stan, "Design and analysis of crossbar circuits for molecular nanoelectronics," In Proceedings of the IEEE Conference on Nanotechnology, pp. 323-327, 2002.
3. L. O. Chua,"Memristor-the missing circuit element. IEEE Trans. On Circuit Theory, 18(5), 507-519, 1971.
4. G. S. Snider, "Memristors as synapses in a neural computing architecture," Memristor and Memristive systems Symposium, Nov 2008.
5. D. B. Strukov, G. S. Snider, D. R. Stewart, S. R. Williams, "The missing memristor found," Nature, vol. 453, no. 7191, pp.80-83, 2008.
6. J. Rajendran, H. Manem and G. S. Rose, "NDR Based Threshold Logic Fabric with Memristive Synapses," In Proceedings of the IEEE Conference on Nanotechnology, Genoa, Italy, 2009.
7. D. B. StrukovandR. S. Williams,"Exponential ionic drift: fast switching and low volatility of thin-film memristors," Applied Physics A, 94(3), 515-519, 2008.
8. G. S. Rose, Y. Tao, J. M. Tour, M. R. Stan et al. "Designing CMOS/Molecular memories while considering device parameter variations," ACM Journal on Emerging Technologies and Computing Systems, vol. 3, no. 1, April 2007.
9. M. Bauer et al. 1995. A Multilevel-Cell 32Mb Flash Memory, In IEEE Int. Solid-State Circuits Conf., Digest of Technical Papers, 132-133.
10. Y. N. Joglekar and S. J. Wolf, "The elusive memristor: properties of basic electrical circuits," Eur. J. Phys., 30(4), 661, 2009.
11. H. Manem and G. S. Rose,"Design Considerations for Variation Tolerant Multilevel CMOS/Nano Memristor Memory," In Proceedings of the ACM Great Lakes Symposium on VLSI, Providence, Rhode Island. 2010.
12. G. Zheng, W. Lu, S. Jin and C. M. Lieber, "Synthesis and Fabrication of High-Performance n-Type Silicon Nanowire Transistors," Adv. Mater. 16, 1890-1893, 2004.