Fabrication and characterization of emerging nanoscale memory

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 65-68

  Kim, SangBum ^a   Zhang, Yuan ^a   Lee, Byoungil ^a   Caldwell, Marissa ^b   Wong, H S Philip ^a  

^a Stanford University   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE PERFORMANCE; DIBLOCK COPOLYMER; E-BEAM LITHOGRAPHY; FUNDAMENTAL LIMITATIONS; FUTURE MEMORY; KEY MATERIALS; MEMORY TECHNOLOGY; MICRO-SCALES; NANO SCALE; NANO-FABRICATION METHODS; NANO-SCALE FABRICATION; NANOCRYSTAL SYNTHESIS; NANOFABRICATION; NANOWIRE GROWTH; NI OXIDE; SEMICONDUCTOR FABRICATION PROCESS; SOLID STATE MEMORIES;

BLOCK COPOLYMERS; FABRICATION; FLASH MEMORY; NANOSTRUCTURED MATERIALS; SEMICONDUCTOR GROWTH; SOLID STATE DEVICES; TECHNOLOGY;

PHASE CHANGE MEMORY;

EID: 70350145009     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117686     Document Type: Conference Paper

References (20)

1. R. Bez and A. Pirovano, "Non-volatile memory technologies: Emerging concepts and new materials," Materials Science in Semiconductor Processing, vol. 7, iss. 4-6, pp. 349-355, 2004.
2. K. Kim and G. Jeong, "Memory technologies in the nano-era : Challenges and opportunities," in ICICDT, 2005, pp. 63-67.
3. G. Muller, T. Happ, M. Kund, G.Y. Lee, N. Nagel, and R. Sezi, "Status and outlook of emerging nonvolatile memory technologies," in IEDM Tech. Dig., 2004, pp.5 67-570.
4. S. Lai, "Current status of the phase change memory and its future," in IEDM Tech. Dig., 2003. pp. 10.1.1-10.1.4.
5. I.G. Baek, M.S. Lee, S. Seo, M.J. Lee, D.H. Seo, D.-S. Suh, J.C. Park, S.O. Park, H.S. Kim, I.K.Yoo, U.-I. Chung, and J.T. Moon, "Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses," in IEDM Tech. Dig., 2004, pp. 587-590.
6. A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, "Scaling analysis of phase-change memory technology," in IEDM Tech. Dig., 2003, 29.6.1-29.6.4.
7. S. Kim and H.-S. P. Wong, "Analysis of temperature in phase change memory scaling," IEEE Elec. Dev. Lett., vol. 28, no. 8, pp. 697-699, 2007.
8. Y.H. Ha, J.H. Yi, H. Horii, J.H. Park, S.H. Joo, S.O. Park, U-In Chung, and J.T. Moon, "An edge contact type cell for phase change RAM featuring very low power consumption," in VLSI Symp. Tech. Dig., 2003, pp. 175-176.
9. F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. Lowrey, A. Lacaita, G. Casagrande, P. Cappelletti, and R. Bez, "Novel μTrench phase-change memory cell for embedded and stand-alone non-volatile memory applications," in VLSI Symp. Tech. Dig., 2004, pp. 18-19.
10. Y.J. Song, K.C. Ryoo, Y.N. Hwang, C.W. Jeong, D.W. Lim, S.S. Park, J.I. Kim, J.H. Kim, S.Y. Lee, J.H. Kong, S.J. Ahn, S.H. Lee, J.H. Park, J.H. Oh, Y.T. Oh, J.S. Kim, J.M. Shin, J.H. Park, Y. Fai, G.H. Koh, G.T. Jeong, R.H. Kim, H.S. Lim, I.S. Park, H.S. Jeong, and K. Kim, "Highly reliable 256Mb PRAM with advanced ring contact technology and novel encapsulating technology," in VLSI Symp. Tech. Dig., 2003, pp. 118-119.
11. Y. C. Chen, C. T. Rettner, S. Raoux, G. W. Burrf, S. H. Chen, R. M. Shelby, M. Salinga, W. P. Risk, T. D. Happ, G. M. McClelland, M. Breitwisch, A. Schrott, J. B. Philipp, M. H. Lee, R. Cheek, T. Nirschl, M. Lamorey, C. F. Chen, E. Joseph, S. Zaidi, B. Yee, H. L. Lung, R. Bergmann, and C. Lam, "Ultra-thin phase-change bridge memory device using GeSb," in IEDM Tech. Dig., 2006, pp. 777-780.
12. S. Lee, Y. Jung, and R. Agarwal, "Highly scalable non-volatile and ultra-low-power phase-change nanowire memory," Nature Nanotechnology Lett.,v. 2, pp. 626-630, 2007.
13. S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, and C. H. Lam, "Phase-change random access memory: A scalable technology," IBM J. Res. & Dev., vol. 52, No. 4/5, pp. 465-479, 2008.
14. C. J. Hawker and T. P. Russell, "Block copolymer lithography: Merging "bottom-up" with "top-down" processes," MRS Bull., v. 30, pp. 952-965, 2005.
15. Y. Zhang, H.-S. P. Wong, S. Raoux, J. N. Cha, C. T. Rettner, L. E. Krupp, T. Topuria, D. J. Milliron, P. M. Rice, and J. L. Jordan-Sweet, "Phase change nanodots arrays fabricated using a self-assembly diblock copolymer approach," Appl. Phys. Lett., v. 91, 013104, 2007.
16. Y. Zhang, S. Raoux, D. Krebs, L. E. Krupp, T. Topuria, M. A. Caldwell, D. J. Milliron, A. Kellock, P. M. Rice, J. L. Jordan-Sweet, and H.-S. P. Wong, "Phase change nanodots patterning using a self-assembled polymer lithography and crystallization analysis," J. Appl. Phys., vol. 104, 074312, 2008.
17. M. Caldwell, S. Raoux, D. Milliron, and H.-S. P. Wong, "Synthesis and characterization of germanium chalcogenide nanoparticles," presented at the Particles 2008 Conference: Particle Synthesis, Characterization, and Particle-Based Advanced Materials, Orlando, Florida, May 10-13, 2008.
18. U. Russo, D. Jelmini, C. Cagli, A. L. Lacaita, S. Spiga, C. Wiemer, M. Perego, and M. Fanciulli, "Conductive-filament switching analysis and self-accelerated thermal dissolution model for reset in NiO-based RRAM," in IEDM Tech. Dig., 2007, pp. 775-778.
19. S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D.-S. Suh, Y. S. Joung, I. K. Yoo, I. R. Hwang, S. H. Kim, I. S. Byun, J.-S. Kim, J. S. Choi, and B. H. Park, "Reproducible resistance switching in polycrystalline NiO films," Appl. Phys. Lett., vol. 85, no. 23, pp. 5655-5657, 2004.
20. K. M. Kim, B. J. Choi, and C. S. Hwang, "Localized switching mechanism in resistive switching of atomic-layer-deposited TiO2 thin films," Appl. Phys. Lett., vol. 90, no. 24, p. 242906, 2007.