Synthesis and optimization of threshold logic networks with application to nanotechnologies

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 904-909

  Zhang, Rui ^a   Gupta, Pallav ^a   Zhong, Lin ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN LOGICS; HIGH-PERFORMANCE SYSTEMS; QUANTUM CELLULAR AUTOMATA (QCA); THRESHOLD LOGIC SYNTHESIZER (TELS); BOOLEAN LOGIC; DESIGN-AUTOMATION TOOLS; LOGIC SYNTHESIS; NANOSCALE DEVICE; QUANTUM CELLULAR AUTOMATON; SYNTHESIS METHODOLOGY; THRESHOLD GATES; THRESHOLD NETWORKS;

ALGORITHMS; BENCHMARKING; BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; HEURISTIC METHODS; LINEAR PROGRAMMING; MAPPING; OPTIMIZATION; PARAMETER ESTIMATION; THEOREM PROVING; THRESHOLD LOGIC; CELLULAR AUTOMATA; COMPUTER AIDED DESIGN; EXHIBITIONS; NANOTECHNOLOGY; TOOLS;

NANOTECHNOLOGY; THRESHOLD LOGIC;

EID: 3042654971     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. "Semiconductor Industries Association Roadmap." http://public.itrs.net
2. D. Goldhaber-Gordon et al., "Overview of nanoelectronic devices," Proc. IEEE, vol. 85, no. 4, pp. 521-540, Apr. 1997.
3. S. Muroga, Threshold Logic and its Applications. New York, NY: John Wiley, 1971.
4. K. J. Chen, K. Maezawa, and M. Yammoto, "InP-based high-performance monostable-bistable transition logic elements (MOBILE's) using integrated multiple-input resonant-tunneling devices," IEEE Electron Device Lett., vol. 17, no. 3, pp. 127-129, Mar. 1996.
5. Z. Kohavi, Switching and Finite Automata Theory. New York, NY: McGraw-Hill, 1978.
6. G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms. Norwell, MA: Kluwer Academic Publishers, 1998.
7. R. O. Winder, "Threshold logic," Ph.D. dissertation, Princeton University, 1962.
8. M. L. Dertouzos, Threshold Logic: A Synthesis Approach. Cambridge, MA: The M.I.T. Press, 1965.
9. G. E. Sobelman and K. Fant, "CMOS circuit design of threshold gates with hysteresis," in Proc. Int. Conf. Circuits & Systems, vol. 2, May 1998, pp. 61-64.
10. V. Beiu, J. M. Quintana, and M. J. Avedillo, "VLSI implementations of threshold logic - A comprehensive survey," Tutorial at Int. Joint Conf. Neural Networks, July 2003.
11. A. L. Oliveira and A. Sangiovanni-Vincentelli, "LSAT - An algorithm for the synthesis of two level threshold gate networks," in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 130-133.
12. E. M. Sentovich et al., "Sequential circuit design using synthesis and optimization," in Proc. Int. Conf. Computer Design, Oct. 1992, pp. 328-333.
13. M. Berkelaar, "Linear programming solver." http://www.cs. sunysb.edu/~algorith/implement/lpsolve/implement.shtml