64 kbit ferroelectric-gate-transistor-integrated NAND flash memory with 7.5 v program and long data retention

Japanese Journal of Applied Physics

Volumn 51, Issue 4 PART 2, 2012, Pages

  Zhang, Xizhen ^a   Takahashi, Mitsue ^a   Takeuchi, Ken ^b   Sakai, Shigeki ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY DESIGN; BIT LINES; CHECKERBOARD PATTERNS; DATA RETENTION; FERROELECTRIC MEMORY ARRAYS; GATE LENGTH; MEMORY CELL; NAND FLASH MEMORY;

HAFNIUM; NAND CIRCUITS; SEMICONDUCTOR STORAGE;

FERROELECTRICITY;

EID: 84860384569     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.51.04DD01     Document Type: Article

References (23)

1. Y. Tarui, T. Hirai, K. Teramoto, H. Koike, and K. Nagashima: Appl. Surf. Sci. 113 (1997) 656.
2. J. F. Scott: Ferroelectric Memories (Springer, Berlin, 2000) Chap. 12, p. 175.
3. H. Ishiwara: Curr. Appl. Phys. 9 (2009) S2.
4. S. Sakai and M. Takahashi: Materials 3 (2010) 4950.
5. S. Sakai: US Patent 7, 226, 795 (2005).
6. S. Sakai and R. Ilangovan: IEEE Electron Device Lett. 25 (2004) 369.
7. Q.-H. Li and S. Sakai: Appl. Phys. Lett. 89 (2006) 222910.
8. Q.-H. Li, M. Takahashi, T. Horiuchi, S. Wang, and S. Sakai: Semicond. Sci. Technol. 23 (2008) 045011.
9. Q.-H. Li, T. Horiuchi, S. Wang, M. Takahashi, and S. Sakai: Semicond. Sci. Technol. 24 (2009) 025012.
10. M. Takahashi and S. Sakai: Jpn. J. Appl. Phys. 44 (2005) L800.
11. L. V. Hai, M. Takahashi, and S. Sakai: Semicond. Sci. Technol. 25 (2010) 115013.
12. L. V. Hai, M. Takahashi, and S. Sakai: Proc. 3rd IEEE Int. Memory Workshop, 2011, p. 175.
13. M. Takahashi, T. Horiuchi, Q.-H. Li, S. Wang, K.-Y. Yun, and S. Sakai: Electron. Lett. 44 (2008) 467.
14. M. Takahashi, S. Wang, T. Horiuchi, and S. Sakai: IEICE Electron. Express 6 (2009) 831.
15. S. Sakai, M. Takahashi, K. Takeuchi, Q.-H. Li, T. Horiuchi, S. Wang, K.-Y. Yun, M. Takamiya, and T. Sakurai: Proc. 23rd IEEE Non-Volatile Semicond. Memory Workshop: 3rd Int. Conf. Memory Technology and Design, 2008, p. 103.
16. S. Wang, M. Takahashi, Q.-H. Li, K. Takeuchi, and S. Sakai: Semicond. Sci. Technol. 24 (2009) 105029.
17. X.-Z. Zhang, K. Miyaji, M. Takahashi, K. Takeuchi, and S. Sakai: Proc. 3rd IEEE Int. Memory Workshop, 2011, p. 155.
18. International Technology Roadmap for Semiconductors 2007 Edition, Process Integration, Devices, and Structures, p. 36.
19. K. Miyaji, S. Noda, T. Hatanaka, M. Takahashi, S. Sakai, and K. Takeuchi: Proc. IEEE Int. Memory Workshop, 2010, p. 42.
20. S. Sakai, M. Takahashi, K. Motohashi, Y. Yamaguchi, N. Yui, and T. Kobayashi: J. Vac. Sci. Technol. A 25 (2007) 903.
21. K. Imamiya, H. Nakamura, T. Himeno, T. Yamamura, T. Ikehashi, K. Takeuchi, K. Kanda, K. Hosono, T. Futatsuyama, K. Kawai, R. Shirota, N. Arai, F. Arai, K. Hatakeyama, H. Hazama, M. Saito, H. Meguro, K. Conley, K. Quader, and J. J. Chen: IEEE J. Solid-State Circuits 37 (2002) 1493.
22. T. Tanaka, Y. Tanaka, H. Nakamura, K. Sakui, H. Oodaira, R. Shirota, K. Ohuchi, F. Masuoka, and H. Hara: IEEE J. Solid-State Circuits 29 (1994) 1366.
23. M. Momodomi, T. Tanaka, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi, and F. Masuoka: IEEE J. Solid-State Circuits 26 (1991) 492.