Operational method of a ferroelectric (Fe)-NAND flash memory array

Semiconductor Science and Technology

Volumn 24, Issue 10, 2009, Pages

  Wang, Shouyu ^a,c   Takahashi, Mitue ^a   Li, Qiu Hong ^a,d   Takeuchi, Ken ^b   Sakai, Shigeki ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c TIANJIN NORMAL UNIVERSITY   (China)

^d HUNAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; CELL ARRAY; GATE FIELD; GATE TRANSISTORS; MEMORY CELL; N-CHANNEL; NAND FLASH MEMORY; OPERATIONAL METHODS; READ CURRENT; RETENTION TIME; TWO-STATE; VERIFICATION TECHNIQUES;

FERROELECTRICITY; FIELD EFFECT TRANSISTORS; HAFNIUM; NAND CIRCUITS; SEMICONDUCTOR STORAGE; TANTALUM;

FLASH MEMORY;

EID: 70350660543     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/24/10/105029     Document Type: Article

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