Basic operation of novel ferroelectric CMOS circuits

Electronics Letters

Volumn 44, Issue 7, 2008, Pages 467-469

  Takahashi, M ^a   Horiuchi, T ^a   Li, Q H ^a   Wang, S ^a   Yun, K Y ^a   Sakai, S ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; FERROELECTRIC DEVICES; FIELD EFFECT TRANSISTORS; LOGIC CIRCUITS; NONDESTRUCTIVE EXAMINATION;

DATA RETENTION; FERROELECTRIC FIELD EFFECT TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 41149127879     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20083230     Document Type: Article

References (5)

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3. Takahashi, M., and Sakai, S.: ' Self-aligned-gate metal/ferroelectric/ insulator/semiconductor field-effect transistors with long memory retention ', Jpn. J. Appl. Phys., 2005, 44, (25), p. L800-L802 0021-4922
4. 2 buffer layers ', Jpn. J. Appl. Phys., 2005, 44, (8), p. 6218-6220 10.1143/JJAP.44.6218 0021-4922
5. 9/Hf-Al-O/Si field-effect transistors at elevated temperatures ', Appl. Phys. Lett., 2006, 89, p. 222910 10.1063/1.2399351 0003-6951