A 0.5 v 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 4, 2012, Pages 1022-1030

  Shikata, Akira ^a   Sekimoto, Ryota ^a   Kuroda, Tadahiro ^a   Ishikuro, Hiroki ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

ADC; CMOS; low voltage; meta stable; reconfigurable DAC; successive approximation; tri level comparator

Indexed keywords

ADC; CMOS; LOW-VOLTAGE; META-STABLE; RE-CONFIGURABLE; SUCCESSIVE APPROXIMATIONS;

APPROXIMATION THEORY; CAPACITORS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; VLSI CIRCUITS;

COMPARATORS (OPTICAL);

EID: 84859722057     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2185352     Document Type: Conference Paper

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