A 12b 11MS/s successive approximation ADC with two comparators in 0.13uμm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 240-241

  Kang, Joshua J ^a,b   Flynn, Michael P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b MARVELL SEMICONDUCTOR INC   (United States)

Author keywords

SAR ADC; Two comparator architecture

Indexed keywords

COMPARATOR ARCHITECTURE; ERROR RATE; POWER CONSUMPTION; PRE-AMPLIFIERS; SAR ADC; SUCCESSIVE-APPROXIMATION ADC; TWO-COMPARATOR ARCHITECTURE;

APPROXIMATION THEORY; ENERGY MANAGEMENT; MULTICARRIER MODULATION; SYNTHETIC APERTURES; VLSI CIRCUITS;

COMPARATORS (OPTICAL);

EID: 70449369454     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. V. Giannini et al, "An 820W 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS," IEEE ISSCC, Feb., 2008.
2. M. van Elzakker et al, "A 1.9W 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC," IEEE ISSCC, Feb., 2008.
3. A. Agnes et al, "A 9.4-ENOB 1V 3.8uμW 100kS/s SAR ADC with Time-Domain Comparator," IEEE ISSCC, Feb., 2008.
4. F. Kuttner, "A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13m CMOS," IEEE ISSCC, Feb., 2002.
5. G. Promitzer, "12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s," IEEE JSSC, pp. 1138-1143, Jul., 2001
6. A. G. W. Venes, and R. J. Plassche, "An 80-MHz, 80-mW, 8-b CMOS Folding A/D Converter with Distributed Track-and-Hold Preprocessing," IEEE JSSC, pp. 1846-1853, Dec., 1996.