A 1.3uμW 0.6V 8.7-ENOB successive approximation ADC in a 0.18uμm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 242-243

  Lee, Seon Kyoo ^a   Park, Seung Jin ^a   Suh, Yunjae ^a   Park, Hong June ^a   Sim, Jae Yoon ^a  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

RAIL-TO-RAIL; REFERENCE VOLTAGES; SUCCESSIVE-APPROXIMATION ADC; SUPPLY VOLTAGES; TIME DOMAIN;

APPROXIMATION THEORY; MULTICARRIER MODULATION;

VLSI CIRCUITS;

EID: 70449376989     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. N. Verma, et. al., "An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes," IEEE JSSC, vol. 42, pp. 1196-1205, Jun. 2007
2. H. C. Hong, et. al., "A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC," IEEE JSSC, vol. 42, pp. 2161-2168, Oct. 2007
3. J. Craninckx, et. al., "A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS," IEEE ISSCC, pp. 246-247, 2007
4. A. Agnes, et. al., "A 9.4-ENOB 1V 3.8W 100kS/s SAR ADC with time-domain comparator," IEEE ISSCC, pp. 246-247, 2008