A 14-bit 100-MS/s digitally calibrated binary-weighted current-steering CMOS DAC without calibration ADC

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 356-359

  Ikeda, Yusuke ^a   Frey, Matthias ^a   Matsuzawa, Akira ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENT MEASUREMENT; ERROR COMPENSATION; ERROR CORRECTION; HYBRID COMPUTERS; MULTICARRIER MODULATION;

BIT RESOLUTION; HIGH-RESOLUTION ADC; SOLID-STATE CIRCUITS CONFERENCE;

CALIBRATION;

EID: 51349107376     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425704     Document Type: Conference Paper

References (4)

1. Y. Cong and R. Geiger, "A 1.5-V 14-b 100MS/s Self-Calibrated DAC," IEEE J. Solid-State Circuits, vol. 38, pp. 2051-2059, Dec. 2003.
2. A. Bugeja and B. S. Song, "A Self-Trimming 14-b 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, pp. 1841-1851, Dec. 2000.
3. H. Chen, J. Lee, J. Weiner, and J. Chen "A 14-bit 150-MS/s CMOS DAC with Digital Background Calibration," in 2006 Symp. VLSI Circuits Dig. Tech. Papers, paper 6-4, June 2006.
4. 2 CMOS DAC," IEEE J. Solid-State Circuits, vol. 36, pp. 1144-1147, July 2001.