A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

European Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 471-474

  Sekimoto, Ryota ^a   Shikata, Akira ^a   Kuroda, Tadahiro ^a   Ishikuro, Hiroki ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; ASYNCHRONOUS CLOCKS; CLOCK GENERATOR; DELAY TIME; DEVICE MISMATCH; FREQUENCY RANGES; LOW VOLTAGES; POWER SUPPLY VOLTAGE; SAR ADC; SETTLING TIME; STANDARD CMOS PROCESS; TEST CHIPS; ULTRA LOW POWER; ULTRA-LOW-VOLTAGE;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CLOCKS; LOW POWER ELECTRONICS; OPTIMIZATION; TIMING CIRCUITS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 82955164353     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2011.6045009     Document Type: Conference Paper

References (8)

1. Simone Gambini and Jan Rabaey, "Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS," IEEE Journal of Solid-State Circuits, Vol.42, No.11, November 2007 pp.2348-2356
2. Marcus Yip and Anantha P. Chandrakasan, "A Resolution-Reconfigurable 5-to-10b 0.4-to-1V Power Scalable SAR ADC," IEEE, ISSCC 2011, pp.190-191
3. Shuo-Wei Michael Chen and Robert W. Brodersen, "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13- m CMOS," IEEE Journal of Solid-State Circuits, Vol.41, No.12, December 2006 pp.2669-2680
4. Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, and Sanroku Tsukamoto, "A 10b 50MS/s 820μW SAR ADC with On-Chip Digital Calibration," IEEE, ISSCC 2010, pp.384-385
5. Brian P. Ginsburg and Anantha P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC," IEEE Journal of Solid-State Circuits, Vol.42, No.4, April 2007 pp.739-747
6. Geert Van der Plas and Bob Verbruggen, "A 150 MS/s 133mW 7 bit ADC in 90 nm Digital CMOS," IEEE Journal of Solid-State Circuits, Vol.43, No.12, December 2008 pp.2631-2640
7. Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, and Hiroki Ishikuro, "A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS," IEEE, VLSI symposium 2011, pp.262-263
8. Pieter Harpe, Cui Zhou, Xiaoyan Wang, Guido Dolmans, and Harmke de Groot, "A 12fJ/Conversion-Step 8bit 10MS/s Asynchronous SAR ADC for Low Energy Radios," IEEE, ESSCIRC 2010, pp.214-217