A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2010, Pages 1015-1018

  Shikata, Akira ^a   Sekimoto, Ryota ^a   Ishikuro, Hiroki ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

Bootstrapped Switch; Energy harvesting; Low voltage; Sample and Hold; Sensor network; Series bootstrapping

Indexed keywords

BOOTSTRAPPED SWITCHES; CIRCUIT OPERATION; CMOS PROCESSS; HIGH LINEARITY; LOW SUPPLY VOLTAGES; LOW VOLTAGES; RISETIMES; RISING TIME; SAMPLE AND HOLD; SAMPLING CAPACITOR; SERIES BOOTSTRAPPING; SIMULATION RESULT; SINGLE PHASE; SUPPLY VOLTAGES; THIRD ORDER HARMONICS;

CMOS INTEGRATED CIRCUITS; ENERGY HARVESTING; SENSOR NETWORKS;

TIMING CIRCUITS;

EID: 79959190760     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2010.5774976     Document Type: Conference Paper

References (3)

1. M. Sato, H. Abe, H. Hamada, M. Majima, T. Kuroda, and H. Ishikuro, " A 90nm CMOS highly linear clock bootstrapped RF sampler operating at wide frequency range of 0.5GHz to 5GHz", IEEE RFIC Symposium 2009, pp.391-394 June, 2009
2. Lei Wang, Junyan Ren, Wenjing Yin, Tingqian Chen, Jun Xu, "A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch", IEEE ISCAS 2007, pp. 1721-1724 May, 2007. (Pubitemid 47448860)
3. Hyunsik Park, Ki Young Nam, David K. Su, Katelijin Vleugels, and Bruce A. Wooley, "A 0.7-V 870-μW Digital-Audio CMOS Sigma-Delta Modulator" , IEEE Journal of Solid-State Circuits, Vol. 44, No. 4, pp1078-1088, April 2009