Improving system energy efficiency with memory rank subsetting

Transactions on Architecture and Code Optimization

Volumn 9, Issue 1, 2012, Pages

  Ahn, Jung Ho ^a   Jouppi, Norman P ^b   Kozyrakis, Christos ^c   Leverich, Jacob ^c   Schreiber, Robert S ^b  

^a Seoul National University   (South Korea)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c STANFORD UNIVERSITY   (United States)

Author keywords

Design; Performance; Reliability

Indexed keywords

CHIP-MULTIPROCESSOR; DIMM MEMORY; DRAM DEVICES; HIGH ENERGY EFFICIENCY; HIGH-RELIABILITY SYSTEMS; IMPROVING SYSTEMS; MAIN-MEMORY; MANY-CORE; MEMORY INTERFACE; MULTI CORE; MULTITHREADED; PERFORMANCE; PROCESSOR PERFORMANCE; PROCESSOR-MEMORY; SIGNIFICANT IMPACTS; SUB-OPTIMAL PERFORMANCE; SYSTEM LEVELS; VLSI PROCESS;

DESIGN; ENERGY EFFICIENCY; RELIABILITY; WIRELESS SENSOR NETWORKS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84859471522     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2133382.2133386     Document Type: Article

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