Packet chaining: Efficient single-cycle allocation for on-chip networks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 83-94

  Michelogiannakis, George ^a   Jiang, Nan ^a   Becker, Daniel ^a   Dally, William J ^a  

^a Stanford University   (United States)

Author keywords

allocation; iterations; on chip networks; packet chaining

Indexed keywords

ALLOCATION; ALLOCATORS; AUGMENTING PATH; CHIP MULTIPROCESSOR; CYCLE TIME; INJECTION RATES; ITERATIONS; NETWORK LATENCIES; NETWORK THROUGHPUT; NUMBER OF CYCLES; ON-CHIP NETWORKS; PACKET CHAINING; PACKET LENGTH; SHORT CYCLE; SHORT PACKETS; SINGLE CYCLE;

NETWORK PERFORMANCE;

BENCHMARKING;

EID: 84858781220     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155631     Document Type: Conference Paper

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