Design of a dynamic priority-based fast path architecture for on-chip interconnects

Proceedings - 15th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnects

Volumn , Issue , 2007, Pages 15-20

  Park, Dongkook ^a   Das, Reetuparna ^a   Nicopoulos, Chrysostomos ^a   Kim, Jongman ^a   Vijaykrishnan, N ^a   Iyer, Ravishankar ^b   Das, Chita R ^a  

^a The Pennsylvania State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE POWER CONSUMPTIONS; CORE SYSTEMS; DYNAMIC PRIORITIES; ENERGY CONSUMPTION; FAST PATH; MINIMAL AREA; NETWORK LATENCIES; NETWORK TRAFFICS; NETWORK-ON-CHIP (NOC) ARCHITECTURE; ON CHIP INTERCONNECTS; OVERALL PERFORMANCE; PATH MANAGEMENT; POWER OVERHEAD; REAL-WORLD APPLICATIONS; ROUTER ARCHITECTURES; SIMULATION RESULTS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARCHITECTURE; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; ENERGY POLICY; INFORMATION MANAGEMENT; INTEGRATED CIRCUITS; INTERNET; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; NETWORK MANAGEMENT; OPTICAL INTERCONNECTS; PIPELINES; PROGRAMMABLE LOGIC CONTROLLERS; ROUTERS; SWITCHING CIRCUITS;

ARCHITECTURAL DESIGN;

EID: 46449125129     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HOTI.2007.1     Document Type: Conference Paper

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