Packet chaining: Efficient single-cycle allocation for on-chip networks

IEEE Computer Architecture Letters

Volumn 10, Issue 2, 2011, Pages 33-36

  Michelogiannakis, George ^a   Jiang, Nan ^a   Becker, Daniel ^a   Dally, William ^a  

^a Stanford University   (United States)

Author keywords

Interconnection architectures; On chip interconnection networks

Indexed keywords

ALLOCATORS; AUGMENTING PATH; CYCLE TIME; INJECTION RATES; INTERCONNECTION ARCHITECTURE; NETWORK LATENCIES; NETWORK ON CHIP; NETWORK THROUGHPUT; NUMBER OF CYCLES; ON-CHIP INTERCONNECTION NETWORK; ON-CHIP NETWORKS; PACKET LENGTH; SHORT CYCLE; SHORT PACKETS; SINGLE CYCLE;

INTERCONNECTION NETWORKS; NETWORK PERFORMANCE; ROUTERS; VLSI CIRCUITS;

BENCHMARKING;

EID: 83555173504     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2011.15     Document Type: Article

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