Active management of timing guardband to save energy in POWER7

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 1-11

  Lefurgy, Charles R ^a   Drake, Alan J ^a   Floyd, Michael S ^a   Allen Ware, Malcolm S ^a   Brock, Bishop ^a   Tierno, Jose A ^a   Carter, John B ^a  

^a IBM   (United States)

Author keywords

critical path; digital phase lock loop; energy efficient; feedback control; POWER7; timing margin

Indexed keywords

CRITICAL PATHS; ENERGY EFFICIENT; PHASE LOCK LOOPS; POWER7; TIMING MARGIN;

BENCHMARKING; CLOCKS; ENERGY CONVERSION; FEEDBACK CONTROL; FIRMWARE; MICROPROCESSOR CHIPS;

TIMING CIRCUITS;

EID: 84858769317     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155622     Document Type: Conference Paper

References (22)

1. Bowman, K.A.; Tschanz, J.W.; Kim, N.S.; Lee, J.C.; Wilkerson, C.B.; Lu, S.-L.L.; Karnik, T.; De, V.K. 2009. Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE Journal of Solid-State Circuits. 44, 1 (Jan. 2009), 49-63. DOI=10.1109/JSSC.2008.2007148.
2. Das, S.; Tokunaga, C.; Pant, S.; Ma, W.-H.; Kalaiselvan, S.; Lai, K.; Bull, D.M.; Blaauw, D.T. 2009. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. IEEE Journal of Solid-State Circuits, 44, 1 (Jan. 2009). IEEE, 32-48. DOI=10.1109/JSSC.2008.2007145.
3. Das, S. 2009. Razor: A Variability-Tolerant Design Methodology for Low-power and Robust Computing. Doctoral Thesis. University of Michigan.
4. Dighe, S.; Vangal, S.; Aseron, P.; Kumar, S.; Jacob, T.; Bowman, K.; Howard, J.; Tschanz, J.; Erraguntla, V.; Borkar, N.; De, V.; Borkar, S. 2010. Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. International Solid-State Circuits Conference Digest of Technical Papers (Feb. 7-11, 2010). ISSCC 2010. IEEE, 174-175. DOI=10.1109/ISSCC.2010.5433997.
5. Drake, A.; Senger, R.; Deogun, H.; Carpenter, G.; Ghiasi, S.; Nguyen, T.; James, N.; Floyd, M.; Pokala, V. 2007. A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. International Solid-State Circuits Conference Digest of Technical Papers (Feb 11-15, 2007). ISSCC 2007. IEEE, 398-399. DOI=10.1109/ISSCC.2007.373462.
6. Ernst, D.; Kim, N.S.; Das, S.; Pant, S.; Rao, R.; Pham, T.; Ziesler, C.; Blaauw, D.; Austin, T.; Flautner, K.; Mudge, T. 2003. Razor: a low-power pipeline based on circuit-level timing speculation. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (Dec 3-5, 2003). MICRO-36. 7-18. DOI=10.1109/MICRO.2003.1253179.
7. Ernst, D.; Das, S.; Lee, S.; Blaauw, D.; Austin, T.; Mudge, T.; Kim, N.S.; Flautner, K. 2004. Razor: circuit-level correction of timing errors for low-power operation. Micro, 24, 6 (Nov.-Dec. 2004), IEEE, 10-20. DOI=10.1109/MM.2004.85.
8. Fick, D.; Liu, N.; Foo, Z.; Fojtik, M.; Seo, J.; Sylvester, D.; Blaauw, D. 2010. In situ delay-slack monitor for highperformance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter. International Solid- State Circuits Conference Digest of Technical Papers (Feb. 7-11, 2010). ISSCC 2010. IEEE, 188-189. DOI=10.1109/ISSCC.2010.5433996.
9. Fischer, T.; Anderson, F.; Patella, B.; Naffziger, S. 2005. A 90nm variable-frequency clock system for a power-managed Itanium®-family processor. International Solid-State Circuits Conference Digest of Technical Papers (Feb. 2005). ISSCC 2005. IEEE. 294-299. DOI=10.1109/ISSCC.2005.1493985.
10. Floyd, M.; Allen-Ware, M.; Rajamani, K.; Brock, B.; Lefurgy, C.; Drake, A.J.; Pesantez, L.; Gloekler, T.; Tierno, J.A.; Bose, P.; Buyuktosunoglu, A. 2011. Introducing the Adaptive Energy Management Features of the Power7 Chip. IEEE Micro, 31, 2, (March-April 2011), 60-75. DOI=10.1109/MM.2011.29.
11. Gupta, M.S.; Rangan, K.K.; Smith, M.D.; Gu-Yeon Wei; Brooks, D. 2008. DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors. In IEEE 14th International Symposium on High Performance Computer Architecture (Salt Lake City, UT, February 2008). HPCA 2008. IEEE, 381-392. DOI=10.1109/HPCA.2008.4658654.
12. IBM. 2011. IBM POWER7 Technology and Systems. IBM Journal of Research and Development. 55, 3 (May-June 2011). DOI=10.1147/JRD.2011.2128750.
13. Intel Corporation. 2009. Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design Guidelines. Reference Number 321736, Revision 002, September, 2009.
14. Isci, C.; Contreras, G.; Martonosi, M. 2006. Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management. In Proceedings of the 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 39). IEEE Computer Society, Washington, DC, USA, 359-370. DOI=10.1109/MICRO.2006.30.
15. Kang, I.; Ethirajan, K.; Severson, M. 2005. Dynamic Voltage Scaling for Portable Devices, U.S. Patent Application 2005/0218871 A1.
16. Keane, J.; Kim, C.H. 2001. An odometer for CPUs. IEEE Spectrum. 48, 5 (May 2011), 28-33. DOI=10.1109/MSPEC.2011.5753241.
17. Meterelliyoz, M.; Goel, A.; Kulkarni, J.P.; Roy, K. 2010. Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replicabias circuit. International Solid-State Circuits Conference Digest of Technical Papers (Feb. 7-11, 2010). ISSCC 2010. IEEE, 186-187. DOI=10.1109/ISSCC.2010.5433991.
18. Reddi, V.; Kanev, S.; Kim, W.; Campanoni, S.; Smith, M.D.; Wei, G.-Y.; Brooks, D. 2010. Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling. In Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 43). IEEE Computer Society, Washington, DC, USA, 77-88. DOI=10.1109/MICRO.2010.35.
19. Rylyakov, A.; Tierno, J.; English, G.; Sperling, M.; Friedman, D. 2008. A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. In Proc. 2008 IEEE Custom Integrated Circuits Conference (Sept. 21-24, 2008). CICC 2008. 431-434. DOI=10.1109/CICC.2008.4672113.
20. Rylyakov, A.; Tierno, J.A. 2010. Method and Apparatus for Low Latency Proportional Path in a Digitally Controlled System. U.S. Patent Application 2010/0017690 A1. January 21, 2010.
21. Tierno, J.A.; Rylyakov, A.V.; Friedman, D.J. 2008. A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. IEEE Journal of Solid-State Circuits. 43, 1 (Jan. 2008), 42-51. DOI=10.1109/JSSC. 2007.910966.
22. Tiwari, A.; Torrellas, J. 2008. Facelift: Hiding and slowing down aging in multicores. In Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture (MICRO 41). IEEE Computer Society, Washington, DC, USA, 129-140. DOI=10.1109/MICRO.2008.4771785.