In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 188-189

  Fick, David ^a   Liu, Nurrachman ^a   Foo, Zhiyoong ^a   Fojtik, Matthew ^a   Seo, Jae Sun ^a   Sylvester, Dennis ^a   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED CMOS; DELAY-SLACK; DESIGN COMPLEXITY; ERROR DETECTION AND CORRECTION; HIGH PERFORMANCE PROCESSORS; IN-SITU; LOCAL VARIATIONS; PVT VARIATIONS; SELF-CALIBRATING; TIME TO DIGITAL CONVERTERS; TIMING MARGIN; TIMING SIGNALS;

ANALOG TO DIGITAL CONVERSION; ERROR CORRECTION; ERROR DETECTION; FREQUENCY CONVERTERS;

TIME MEASUREMENT;

EID: 77952234485     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433996     Document Type: Conference Paper

References (3)

1. A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Nguyen, N. James, M. Floyd, V. Pokala, "A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor," International Solid-State Circuits Conference, pp. 398-399, 2007.
2. K. Woo, S. Meninger, T. Xanthopoulos, E. Crain, D. Ha, D. Ham, "Dual-DLL Based CMOS All-Digital Temperature Sensor for Microprocessor Thermal Monitoring," International Solid-State Circuits Conference, pp. 68-71, 2009.
3. D. Blaauw, S. Kalaiselvan, K. Lai, W-H. Ma, S. Pant, C. Tokunaga, S. Das, D. Bull, "Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance," International Solid-State Circuits Conference, pp. 400-401, 2008.