SCOPUS 정보 검색 플랫폼

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 174-175

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

(12) Dighe, Saurabh a Vangal, Sriram a Aseron, Paolo a Kumar, Shasi b Jacob, Tiju b Bowman, Keith a Howard, Jason a Tschanz, James a Erraguntla, Vasantha b Borkar, Nitin a De, Vivek a Borkar, Shekhar a

a INTEL CORPORATION (United States)

b INTEL TECHNOLOGY INDIA PVT LTD (India)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL SIMULATION; CORE PROCESSORS; DYNAMIC CORES; DYNAMIC VOLTAGE; FREQUENCY-SCALING; LEAKAGE POWER; MANY-CORE; NETWORK ON CHIP; POWER GATINGS; SINGLE INSTRUCTION/MULTIPLE DATUM; STATISTICAL VARIATIONS; TECHNOLOGY SCALING; V/F CONTROL; WITHIN DIES; WITHIN-DIE VARIATIONS;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIES; ENERGY EFFICIENCY; VLSI CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 77952165111 PISSN: 01936530 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISSCC.2010.5433997 Document Type: Conference Paper

Times cited : (47)

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4
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.