Effects of Cu surface roughness on TDDB for direct polishing ultra-low k dielectric Cu interconnects at 40 nm technology node and beyond

Microelectronic Engineering

Volumn 92, Issue , 2012, Pages 115-118

  Lin, W C ^a   Lin, Jack ^a   Tsai, T C ^a   Hsu, C M ^a   Liu, C C ^a   Lin, J F ^a   Hwang, C C ^a   Wu, J Y ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

Cu surface roughness on TDDB influence by CMP

Indexed keywords

BACK END OF LINES; CU SURFACES; CU-INTERCONNECTS; GAP CONDITIONS; METAL CAPPING LAYERS; METAL LINE; MICROSCRATCHES; RELIABILITY PERFORMANCE; TECHNOLOGY NODES; TEST STRUCTURE; TIME-DEPENDENT DIELECTRIC BREAKDOWN; ULTRA-LOW-K DIELECTRICS;

CHEMICAL MECHANICAL POLISHING; CLEANING; DIELECTRIC MATERIALS; NANOTECHNOLOGY; POLISHING;

SURFACE ROUGHNESS;

EID: 84858297174     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2011.04.057     Document Type: Conference Paper

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