Copper-line topology impact on the reliability of sioch low-k for the 45-nm technology node and beyond

IEEE Transactions on Device and Materials Reliability

Volumn 9, Issue 2, 2009, Pages 120-127

  Vilmay, Maxime ^a   Roy, David ^a   Monget, Cedric ^a   Volpi, Fabien ^b   Chaix, Jean Marc ^b  

^a STMICROELECTRONICS   (France)

^b CNRS   (France)

Author keywords

Geometrical effect; Low k dielectrics; Microelectronics; Reliability; Roughness

Indexed keywords

ANALYTICAL MODEL; COPPER INTERCONNECTS; COPPER LINES; CRITICAL DIMENSION; FIRST-ORDER; GEOMETRICAL EFFECT; HIGH-VOLTAGE STRESS; LINE EDGE ROUGHNESS; LINE SHAPE; LINE TOPOLOGY; LINE-TO-LINE SPACING; LOW-K DIELECTRICS; NODE TECHNOLOGY; NOMINAL VOLTAGE; OPERATIONAL VOLTAGE; PRODUCT LIFETIME; ROUGHNESS; SPACING UNIFORMITY; TECHNOLOGY NODES; TOPOLOGICAL EFFECTS; WEIBULL SHAPE;

COPPER; ELECTRIC POTENTIAL; MICROELECTRONICS; NANOTECHNOLOGY; OPTICAL INTERCONNECTS; RELIABILITY;

DIELECTRIC MATERIALS;

EID: 67650337585     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2009.2020089     Document Type: Conference Paper

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