The TDDB study of post-CMP cleaning effect for L40 direct polished porous low K dielectrics Cu interconnect

ECS Transactions

Volumn 33, Issue 10, 2010, Pages 99-105

  Hsu, C L ^a,b   Lin, W C ^b   Hsu, C W ^b   Lin, J C ^b   Tsai, T C ^b   Huang, C C ^b   Wu, J Y ^b   Perng, D C ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CLEANING; DIELECTRIC MATERIALS; LOW-K DIELECTRIC; POLISHING; SURFACE ROUGHNESS;

CU INTERCONNECT; CU SURFACES; DUAL DAMASCENE INTERCONNECTS; FEATURE SIZES; FILM PROPERTIES; POLISHED SURFACES; POROUS LOW-K DIELECTRICS; POST-CMP CLEANING;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84863157817     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3489050     Document Type: Conference Paper

References (7)

1. C.L. Hsu, et al., in Proc. IRPS, pp. 918-921 (2010).
2. C.L. Hsu, et al., in Proc. IITC, pp. 140-142 (2009).
3. F. Chen, et al., IEEE Trans. Electr. Dev., vol. 56, pp. 2-12 (2009).
4. G. S. Haase, in Proc. IRPS, pp. 556-565 (2008).
5. M. Vilmay, IEEE Trans. Electr. Dev. and Mater. Reliab., vol. 9, pp. 120-127 (2009).
6. J. Kim, et al., in Proc. IRPS, pp. 399-404 (2007).
7. M.N. Chang, in Proc. IRPS, pp. 619-623 (2009).