Deterministic IDDQ diagnosis using a net activation based model

Proceedings - International Test Conference

Volumn , Issue , 2011, Pages

  Kun, András ^a   Arnold, Ralf ^a   Heinrich, Peter ^a   Maugard, Guenole ^a   Tang, Huaxing ^b   Cheng, Wu Tung ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION TOOLS; AUTOMOTIVE BUSINESS; AUTOMOTIVE DESIGNS; DEFECTIVE PARTS PER MILLIONS; DIAGNOSIS METHODS; DIGITAL CIRCUITRY; FAST SIMULATION; MULTIPLE DEFECTS; PRODUCTION FAILURE; QUALITY TARGETS; QUIESCENT SUPPLY CURRENT; TEST COVERAGE; TEST METHOD; VOLUME DIAGNOSIS;

AUTOMATIC TEST PATTERN GENERATION;

EID: 84857592113     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2011.6139175     Document Type: Conference Paper

References (19)

1. R. Arnold, M. Feuser, H.-U. Wedekind, T. Bode, "Experiences with Implementation of IDDQ Test for Identification and Automotive Products", Proc. of ITC, 1997, pp. 127-135
2. K. Baker, S.C. Verhelst, "IDDQ Testing because Zero-defects isn't enough: A Philips Perspective", Proc. of ITC, 1990, pp. 253-254
3. C.F. Hawkins et al., "Defect Classes - An Overdue Paradigm for CMOS IC Testing", Proc. of ITC, 1995, pp 413-425
4. P. Maxwell et al., "IDDQ and AC Scan: The War against Unmodelled Defects", Proc. of ITC, 1996, pp 250-258
5. M Schmid, H. Manhaeve, "Improving Automotive IC Quality. A Case Study on the Implementation of Advanced IDDQ Strategies Targeting Product Quality Improvement, Burn-in Elimination and Test Cost Reduction", DBT 2006
6. Alessandra Fudoli, Alberto Ascagni, Davide Appello, Hans Manhaeve, "A Practical Evaluation of IDDQ Test Strategies for Deep Submicron Production Test Application. Experiences and Targets from the Field", ETW 2003
7. Peter Maxwell, Pete O.Neill, Rob Aitken, Roland Dudley, Neal Jaarsma, Minh Quach, Don Wisema, "Current Ratios: A Self-Scaling Technique for Production IDDQ Testing", ITC 1999
8. Heiko Ahrens, Rolf Schlagenhaft, Helmut Lang, V. Srinivasan, Enrico Bruzzano, "DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG", ITC 2008
9. Phil Nigh, Dave Vallett, Atul Patel, Jason Wright, "Failure Analysis of Timing and IDDq-only failures form the SEMATECH Test Methods Experiment", ITC98
10. Phil Nigh, Anne Gattiker, "Random and SystematicDefect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions", ITC 2004
11. Anne E. Gattiker and Wojciech Maly, "Current Signatures: Application", Proc. of ITC, pp. 156-165, 1997
12. ]Y. Hariri and C. Thibeault, "Bridging fault diagnostic tool based on DeltaIDDQ probabilistic signatures, circuit layout parasitic and logic errors", IET Comput. Digit. Tech., 2007, Vol. 1, No 6, pp. 694-705 (Pubitemid 350025563)
13. M. Laisne, et-al, "Verification and Debugging of IDDQ Test of Low Power Chips", ITC 2007
14. Doug Heaberlin, "The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and Resolution", ITC 2006
15. Phil Nigh, Donato Forlenza, Franco Motika, "Application and Analysis of IDDQ Diagnostic Software", Proc. of ITC, pp. 319-327, 1997
16. A. Leininger, P. Muhmentaler, W.-T. Cheng, N. Tamarapalli, W. Yang, and H. Tsai, "Compression mode diagnosis enables high volume monitoring diagnosis flow", Proc. of ITC, paper 7.3, 2005
17. R. C. Aitken, "Fault Location with Current Monitoring," Proc. of ITC, pp. 623-632, 1991
18. D.B.Lavo, T.Larrabee, J. E.Colburn "Eliminating the Ouija Board: Automatic Threshold and Probabilistic Iddq Diagnosis", Proc of ITC, pp. 1065-1071, 1999
19. ddq-based diagnosis at very low voltage (VLV) for bridging defects; Electronic Letters Volume 43, Issue 5, pp.25-26, 2007