Verification and debugging of IDDQTest of low power chips

Proceedings - International Test Conference

Volumn , Issue , 2007, Pages

  Laisne M ^a   Nguyen, T ^a   Zuo, S ^a   Pan, X ^a   Cui, H ^a   Bai, C ^a   Street, A ^a   Parley, M ^a   Agrawal, N ^a   Sundararaman, K ^a  

^a QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; PROBLEM SOLVING; PROGRAM DEBUGGING; VERIFICATION;

CELL CONSTRAINTS; LOW POWER CHIPS; NET VALUE ANALYSIS;

MICROPROCESSOR CHIPS;

EID: 39749186091     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2007.4437628     Document Type: Conference Paper

References (16)