DiDi: Mitigating the performance impact of TLB shootdowns using a shared TLB directory

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2011, Pages 340-349

  Villavieja, Carlos ^a,b   Karakostas, Vasileios ^a,b   Vilanova, Lluis ^a,b   Etsion, Yoav ^b   Ramirez, Alex ^a,b   Mendelson, Avi ^d   Navarro, Nacho ^a,b   Cristal, Adrián ^a,c   Unsal, Osman S ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

^c ARTIFICIAL INTELLIGENCE RESEARCH INSTITUTE IIIA CSIC   (Spain)

^d MICROSOFT RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTIPROCESSOR; MACHINE CYCLE; MEMORY ACCESS; MODERN ARCHITECTURES; PAGE TABLE; PERFORMANCE IMPACT; PERFORMANCE SCALABILITY; SOFTWARE-BASED; TRANSLATION LOOKASIDE BUFFER;

MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS; PARALLEL ARCHITECTURES; SCALABILITY;

BUFFER STORAGE;

EID: 84856515634     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2011.65     Document Type: Conference Paper

References (26)

1. M. Abadi, T. Harris, and M. Mehrara. Transactional Memory With Strong Atomicity Using Off-The-Shelf Memory Protection Hardware. SIGPLAN Not., 44:185-196, February 2009.
2. Apache Software Foundation. The Apache Test Project. http://httpd.apache. org/test/, 2011.
3. D. H. Bailey, L. Dagum, E. Barszcz, and H. D. Simon. NAS Parallel Benchmark Results. In Proceedings of the 1992 ACM/IEEE conference on Supercomputing, Supercomputing, pages 386-393, 1992.
4. K. Barker, K. Davis, A. Hoisie, D. J. Kerbyson, M. Lang, S. Pakin, and J. C. Sancho. A Performance Evaluation of the Nehalem Quadcore Processor for Scientific Computing. Parallel Processing Letters, December 2008.
5. A. Baumann, P. Barham, P.-E. Dagand, T. Harris, R. Isaacs, S. Peter, T. Roscoe, A. Schüpbach, and A. Singhania. The multikernel: a new OS architecture for scalable multicore systems. In Symp. on Operating Systems Principles (SOSP), pages 29-44, 2009.
6. A. Bhattacharjee and M. Martonosi. Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors. In Intl. Conf. on Parallel Arch. and Compilation Techniques, pages 29-40, 2009.
7. A. Bhattacharjee and M. Martonosi. Inter-core Cooperative TLB For Chip MultiProcessors. In Intl. Conf. on Arch. Support for Programming Languages & Operating Systems, pages 359-370, 2010.
8. B. A. Bhattacharjee, D. Lustig, and M. Martonosi. Shared Last- Level TLBs for Chip Multiprocessors. In Symp. on High-Performance Computer Architecture (HPCA), 2011.
9. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In Intl. Conf. on Parallel Arch. and Compilation Techniques, October 2008.
10. D. L. Black, R. F. Rashid, D. B. Golub, and C. R. Hill. Translation Lookaside Buffer Consistency: A Software Approach. Computer Architecture News, 17(2):113-122, 1989.
11. C. Cao Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In IISWC '08: Proceedings of The IEEE International Symposium on Workload Characterization, September 2008.
12. D. Dice, O. Shalev, and N. Shavit. Transactional Locking II. In DISC, pages 194-208, 2006. (Pubitemid 44849711)
13. Y. Etsion, D. Tsafrir, and D. G. Feitelson. Effects of Clock Resolution on the Scheduling of Interactive and Soft Real-Time Processes. In Intl. Conf. on Measurement & Modeling of Computer Systems (SIGMETRICS), pages 172-183, Jun 2003.
14. P.-M. Fournier, M. Desnoyers, and M. R. Dagenais. Combined Tracing of the Kernel and Applications with LTTng. In Linux Symposium, Jul 2009.
15. I. Gelado, J. H. Kelm, S. Ryoo, S. S. Lumetta, N. Navarro, and W. mei W. Hwu. CUBA: An Architecture For Efficient CPU/Co-Processor Data Communication. In ACM Intl. Conf. on Supercomputing, pages 299-308, 2008.
16. H. P. Hofstee. Power Efficient Processor Architecture and The Cell Processor. In Symp. on High-Performance Computer Architecture (HPCA), pages 258-262, 2005. (Pubitemid 41731505)
17. B. L. Jacob and T. N. Mudge. A Look At Several Memory Management Units, TLB-refill Mechanisms, And Page Table Organizations. Operating Systems Review, 32(5):295-306, 1998.
18. M. Martin, C. Blundell, and E. Lewis. Subtleties of Transactional Memory Atomicity Semantics. IEEE Computer Architecture Letters, 5:17-, July 2006.
19. N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi. Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro, 28(1):69-79, 2008. (Pubitemid 351447393)
20. C. Ranger, R. Raghuraman, A. Penmetsa, G. Bradski, and C. Kozyrakis. Evaluating MapReduce for Multi-core and Multiprocessor Systems. In Symp. on High-Performance Computer Architecture (HPCA), pages 13- 24, 2007. (Pubitemid 47208148)
21. R. Rashid, A. Tevanian, M. Young, D. Golub, R. Baron, D. Black, W. Bolosky, and J. Chew. Machine-Independent Virtual Memory Management For Paged Uniprocessor And Multiprocessor Architectures. Computer Architecture News, 15(5):31-39, 1987. (Pubitemid 18538631)
22. A. Rico, F. Cabarcas, A. Quesada, M. Pavlovic, A. J. Vega, C. Villavieja, Y. Etsion, and A. Ramirez. Scalable Simulation of Decoupled Accelerator Architectures. Technical Report UPC-DAC-RR-2010-14, Universitat Politècnica de Catalunya, Jun 2010.
23. B. F. Romanescu, A. R. Lebeck, D. J. Sorin, and A. Bracy. UNified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All. In Symp. on High-Performance Computer Architecture (HPCA), 2010.
24. B. Rosenburg. Low-Synchronization Translation Lookaside Buffer Consistency In Large-Scale Shared-Memory Multiprocessors. In Symp. on Operating Systems Principles (SOSP), pages 137-146, 1989. (Pubitemid 20640867)
25. S. Srikantaiah and M. Kandemir. Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors. In Intl. Symp. on Microarchitecture, 2010.
26. P. J. Teller, R. Kenner, and M. Snir. TLB Consistency On Highly- Parallel Shared-Memory Multiprocessors. In Annual Hawaii Intl. Conf. On System Sciences (Architecture Track), pages 184-193, 1988. (Pubitemid 18598818)