Unified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2010, Pages

  Romanescu, Bogdan F ^a   Lebeck, Alvin R ^a   Sorin, Daniel J ^a   Bracy, Anne ^b  

^a DUKE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; SUPERCOMPUTERS;

CACHE COHERENCE PROTOCOLS; COHERENCE PROTOCOL; DATA CACHES; MULTI-CORE PROCESSOR; PERFORMANCE PENALTIES;

COMPUTER ARCHITECTURE;

EID: 77952572235     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/hpca.2010.5416643     Document Type: Conference Paper

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