Transactional memory with strong atomicity using off-the-shelf memory protection hardware

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP

Volumn , Issue , 2009, Pages 185-195

  Abadi, Martín ^a,b   Harris, Tim ^a   Mehrara, Mojtaba ^a,c  

^a MICROSOFT RESEARCH   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Algorithms; Languages; Performance

Indexed keywords

LANGUAGES; LEVEL MECHANISM; MEMORY ACCESS; MEMORY PROTECTION; OBJECT PLACEMENT; PATHOLOGICAL CASE; PERFORMANCE; PHASE CHANGE; POOR PERFORMANCE; TRANSACTIONAL MEMORY;

LINGUISTICS; STORAGE ALLOCATION (COMPUTER);

PARALLEL PROGRAMMING;

EID: 67650076847     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1504176.1504203     Document Type: Conference Paper

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