Development of a novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated systems

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 383-387

  Nagarajan, Ranganathan ^a   Liao, Ebin ^a   Lee, Dayong ^b   Soh, Chee Seng ^b   Prasad, Krishnamachar ^b   Balasubramanian, N ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER PLATING; DEPOSITION; DIELECTRIC MATERIALS; ETCHING; METALLIZING;

3-D INTEGRATED SYSTEMS; COPPER DIFFUSION BARRIERS; COPPER SEED METALLIZATION;

SEMICONDUCTING SILICON;

EID: 33845564746     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645674     Document Type: Conference Paper

References (11)

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