Structural design and optimization of 65nm Cu/low-k flipchip package

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2007, Pages 488-492

  Ong, Jimmy ^a,b,c   Zhang, Xiaowu ^a   Kripesh, V ^a   Lim, Yeow Kheng ^b   Yeo, David ^b   Chan, Kai Chong ^b   Tan, Juan Boon ^b   Hsia, Liang Choo ^b   Sohn, Dong Kyun ^b   Tay, Andrew ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; CHIP SCALE PACKAGES; COPPER; DIES; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS INDUSTRY; ELECTRONICS PACKAGING; INTEGRATED CIRCUITS; MATERIALS SCIENCE; METALS; MOLECULAR BEAM EPITAXY; RECONSTRUCTION (STRUCTURAL); RELIABILITY; RELIABILITY ANALYSIS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; SEMICONDUCTOR MATERIALS; STRESSES; STRUCTURAL DESIGN; STRUCTURAL OPTIMIZATION; TECHNOLOGY;

DESIGN AND OPTIMIZATION; DESIGN GUIDELINES; FLIP-CHIP PACKAGING; LOW-K DIELECTRIC MATERIALS; LOW-K MATERIALS; LOW-MODULUS; MECHANICAL FAILURES; PACKAGING TECHNOLOGIES; PARAMETRIC STUDIES; PLANE STRAINS; SEMICONDUCTOR INDUSTRIES; SOLDER BUMPING; SUBSTRATE THICKNESSES; UNDERFILL; UNDERFILLS;

DIELECTRIC MATERIALS;

EID: 50049096152     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2007.4469679     Document Type: Conference Paper

References (16)

1. K.-B. Cha, Y.-G. Kim, T.-K. Kang, D.-S. Kang and S.-D. Baek, "Ultra-Thin and Crack-Free Bottom Leaded Plastic (BLP) Package Design," Proc. 45th Electronic Components and Technology Conference, Las Vegas, May 22, 1995, pp. 224-228.
2. T.-G. Kang, Y.-G. Kim, H.-S. Chun, K.-B. Cha, S.-J. Heo and M.-J. Shin, "Bottom Leaded Plastic (BLP) Package: A New Design with Low-Cost Adhesive Material," Proc. NEPCON-West'97, 1997, pp. 1061-1068Guotao Wang, Steven Groothuis and Paul S. Ho, "Effect of Packaging on Interfacial Cracking in Cu/ Low k Damascene Structures" Proc. of ECTC, 2003, pp. 727-732.
3. Seung Wook Yoon, David Wirtasa, Samuel Lim, V. Ganesh, *Akella Viswanath, Vaidyanathan Kripesh and Mahadevan K. Iyer. "PEDL (Polymer Encapsulated Dicing Line) Technology for Copper/Low-k Dielectrics Interconnect," 2005 Electronics Packaging Technology Conference.
4. Seung Wook Yoon, Vaidyanathan Kripesh, Li Hongyu,Li Chao Yong, Su Yong Ji Jeffrey and Mahadevan K. Iyer, "Flipchip Bump Integrity with Copper/Ultra Low-k Dielectrics for fine pitch Flipchip Packaging", Proceeding of the 54th Electronic Components Technology Conference(ECTC), Las Vegas, US (2004).
5. Lei L. Mercado, Senior Member, IEEE, Cindy Goldberg, Shun-Meen Kuo, Tien-Yu (Tom) Lee, Associate Member, IEEE, and Scott K. Pozder. "IEEE transactions on device and materials reliability", Vol. 3, no. 4, December 2003.
6. Lei Mercado, Cindy Goldberg*, Shun-Meen Kuo. "A Simulation Method for Predicting Packaging Mechanical Reliability with Low K Dielectrics" Motorola Final Manufacturing Technology Center, Tempe and Motorola Advanced Products Research and Development Laboratories, Austin Report
7. Y.-G. Kim, K.-S. Choi, and S. Choi, "Solder Joint Reliability of the Leaded and Leadless Packages: New BLP Design," Proc. Semicon-West'97, San Jose, 1997, pp. 1-9.
8. Y.-G Kim, B. Han, S. Choi and M.-K. Kim, "Bottom Leaded Plastic (BLP) Package: A New Design with Enhanced Solder Joint Reliability," Proc. 46th Electronic Components and Technology Conference, Orlando, May 29, 1996, pp. 448-452.
9. K.-S. Choi, S. Choi, Y. -G. Kim, and K.-Y. Cho, "Solder Joint Reliability of the BLP (Bottom-Leaded Plastic) Package", Proc. Semicon-Korea'97, Seoul, Feb. 6, 1997, pp. 11127-11132
10. J. Kloeser et al., "Low-cost flip-chip bonding on FR-4 boards," Circuit World, vol. 22, no. 1, pp. 18-21, Oct. 1995.
11. Rai et al., "COB (chip on board) technology: Flip chip bonding onto ceramic substrates and PWB (printed wiring boards)," in Proc. 1990 IntSymp. Microelectron., 1990, pp. 474-481.
12. D. Suryanarayana, R. Hsiao, T. P. Gall, and J. J. McCreary, "Enhancement of flip-chip fatigue life by encapsulation," IEEE Trans. Comp. Hybrids, Manufact Technol, vol. 14, pp. 218-223, 1991
13. Fan, X.-J., Wang, H. B., and Lim, T. B., "Investigation of the Underfill Delamination and Cracking in Flip-Chip Modules Under Temperature Cyclic Loading," IEEE Transactions on Components and Packaging Technologies, Vol. 24(1), pp. 84-91, 2001.
14. Mercado, L. L., Sarihan, V., and Hauck, T., "An Analysis of Interface Delamination in Flip-Chip Packages, "P roceedings of the 50th Electronic Components and Technology Conference, pp. 1332-1337, Las Vegas, NV, May 21-24, 2000.
15. Cheng, Z, Xu, B., Zhang, Q., Cai, X., Huang, W., and Xie, X., "Underfill Delamination Analysis of Flip Chipon Low-Cost Board," International Symposium on Electronic Materials and Packaging (EMAP), pp. 280-285, November 19-22, 2001
16. Chen, L., Zhang, Q, Wang, G., Xie, X., and Cheng, Z., "The Effects of Underfill and Its Material Models on Thermomechanical Behaviors of a Flip Chip Package," IEEE Transactions on Advanced Packaging, Vol. 24(1), pp. 17-24, 2001.