-
1
-
-
84887213363
-
-
Algotronix Ltd.: AES G3 Data Sheet: Xilinx Edition, October Available at
-
Algotronix Ltd.: AES G3 Data Sheet: Xilinx Edition, October 2007. Available at http://www. algotronix-store. com/kb_results. asp?ID=7.
-
(2007)
-
-
-
2
-
-
84887212858
-
-
ANSI X9. 62-2005.: American National Standard X9. 62: The Elliptic Curve Digital Signature Algorithm (ECDSA)
-
ANSI X9. 62-2005.: American National Standard X9. 62: The Elliptic Curve Digital Signature Algorithm (ECDSA) (2005).
-
(2005)
-
-
-
3
-
-
85057426796
-
-
Boca Raton: Chapman and Hall/CRC
-
Avanzi R. M., Cohen H., Doche C., Frey G., Lange T., Nguyen K., Vercauteren F.: Handbook of Elliptic and Hyperelliptic Curve Cryptography. Chapman and Hall/CRC, Boca Raton (2005).
-
(2005)
Handbook of Elliptic and Hyperelliptic Curve Cryptography
-
-
Avanzi, R.M.1
Cohen, H.2
Doche, C.3
Frey, G.4
Lange, T.5
Nguyen, K.6
Vercauteren, F.7
-
4
-
-
0035390239
-
High radix montgomery modular exponentiation on reconfigurable hardware
-
Blum T., Paar C.: High radix montgomery modular exponentiation on reconfigurable hardware. IEEE Trans. Comput. 50(7), 759-764 (2001).
-
(2001)
IEEE Trans. Comput.
, vol.50
, Issue.7
, pp. 759-764
-
-
Blum, T.1
Paar, C.2
-
5
-
-
45449086847
-
Implementation of the AES-128 on Virtex-5 FPGAs
-
S. Vaudenay (Ed.), Berlin: Springer
-
Bulens P., Standaert F., Quisquater J.-J., Pellegrin P., Rouvroy G.: Implementation of the AES-128 on Virtex-5 FPGAs. In: Vaudenay, S. (ed.) Proceedings of First International Conference on Cryptology in Africa-AFRICACRYPT 2008. LNCS Series, vol. 5023, pp. 16-26. Springer, Berlin (2008).
-
(2008)
Proceedings of First International Conference on Cryptology in Africa-AFRICACRYPT 2008. LNCS Series
, vol.5023
, pp. 16-26
-
-
Bulens, P.1
Standaert, F.2
Quisquater, J.-J.3
Pellegrin, P.4
Rouvroy, G.5
-
6
-
-
48149104394
-
Reconfigurable memory-based AES co-processor
-
Chaves, R., Kuzmanov, G., Vassiliadis, S., Sousa, L.: Reconfigurable memory-based AES co-processor. In: Proceedings of the Workshop on Reconfigurable Architectures (RAW 2006), p. 192 (2006).
-
(2006)
Proceedings of the Workshop on Reconfigurable Architectures (RAW 2006)
, pp. 192
-
-
Chaves, R.1
Kuzmanov, G.2
Vassiliadis, S.3
Sousa, L.4
-
7
-
-
35248880566
-
Very compact FPGA Implementation of the AES algorithm
-
C. D. Walter, Ç. K. Koç, and C. Paar (Eds.), Berlin: Springer
-
Chodowiec P., Gaj K.: Very compact FPGA Implementation of the AES algorithm. In: Walter, C. D., Koç, Ç. K., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003). LNCS, vol. 2779, pp. 319-333. Springer, Berlin (2003).
-
(2003)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003). LNCS
, vol.2779
, pp. 319-333
-
-
Chodowiec, P.1
Gaj, K.2
-
8
-
-
10444273896
-
Exponentiation cryptosystems on the IBM PC
-
Comba P. G.: Exponentiation cryptosystems on the IBM PC. IBM Syst. J. 29(4), 526-538 (1990).
-
(1990)
IBM Syst. J.
, vol.29
, Issue.4
, pp. 526-538
-
-
Comba, P.G.1
-
10
-
-
2642517965
-
An FPGA Implementation of a GF(p) ALU for encryption processors
-
Daly A., Marnane W., Kerins T., Popovici E.: An FPGA Implementation of a GF(p) ALU for encryption processors. Elsevier-Microprocess. Microsyst. 28(5-6), 253-260 (2004).
-
(2004)
Elsevier-Microprocess. Microsyst.
, vol.28
, Issue.5-6
, pp. 253-260
-
-
Daly, A.1
Marnane, W.2
Kerins, T.3
Popovici, E.4
-
11
-
-
33846260842
-
High-speed hardware implementations of Elliptic Curve Cryptography: a survey
-
de Dormale G. M., Quisquater J.-J.: High-speed hardware implementations of Elliptic Curve Cryptography: a survey. J. Syst. Archit. 53(2-3), 72-84 (2007).
-
(2007)
J. Syst. Archit.
, vol.53
, Issue.2-3
, pp. 72-84
-
-
de Dormale, G.M.1
Quisquater, J.-J.2
-
13
-
-
60349118477
-
DSPs, BRAMs and a pinch of logic: new recipes for AES on FPGAs
-
IEEE Computer Society, April 2008. Source code available at
-
Drimer, S., Güneysu, T., Paar, C.: DSPs, BRAMs and a pinch of logic: new recipes for AES on FPGAs. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), pp. 99-108. IEEE Computer Society, April 2008. Source code available at: http://www. cl. cam. ac. uk/~sd410/aes/.
-
(2008)
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
, pp. 99-108
-
-
Drimer, S.1
Güneysu, T.2
Paar, C.3
-
15
-
-
84887213367
-
-
ECRYPT. eBATS.: ECRYPT Benchmarking of Asymmetric Systems, March Available at
-
ECRYPT. eBATS.: ECRYPT Benchmarking of Asymmetric Systems, March 2007. Available at http://www. ecrypt. eu. org/ebats/.
-
(2007)
-
-
-
16
-
-
0035425820
-
An FPGA-based Performance evaluation of the AES block cipher candidate algorithm finalists
-
Elbirt A. J., Yip W., Chetwynd B., Paar C.: An FPGA-based Performance evaluation of the AES block cipher candidate algorithm finalists. IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 9(4), 545-557 (2001).
-
(2001)
IEEE Trans. Very Large Scale Integr. Syst. (VLSI)
, vol.9
, Issue.4
, pp. 545-557
-
-
Elbirt, A.J.1
Yip, W.2
Chetwynd, B.3
Paar, C.4
-
17
-
-
84874800178
-
A public key cryptosystem and a signature scheme based on discrete logarithms
-
Elgamal T.: A public key cryptosystem and a signature scheme based on discrete logarithms. IEEE Trans. Inform. Theory 31(4), 469-472 (1985).
-
(1985)
IEEE Trans. Inform. Theory
, vol.31
, Issue.4
, pp. 469-472
-
-
Elgamal, T.1
-
18
-
-
84944872607
-
Two methods of Rijndael implementation in reconfigurable hardware
-
Ç. K. Koç, D. Naccache, and C. Paar (Eds.), Berlin: Springer
-
Fischer V., Drutarovský M.: Two methods of Rijndael implementation in reconfigurable hardware. In: Koç, Ç. K., Naccache, D., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS, vol. 2162, pp. 77-92. Springer, Berlin (2001).
-
(2001)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS
, vol.2162
, pp. 77-92
-
-
Fischer, V.1
Drutarovský, M.2
-
20
-
-
27244443921
-
AES on FPGA from the fastest to the smallest
-
J. R. Rao and B. Sunar (Eds.), Berlin: Springer
-
Good T., Benaissa M.: AES on FPGA from the fastest to the smallest. In: Rao, J. R., Sunar, B. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005), LNCS, vol. 3659, pp. 427-440. Springer, Berlin (2005).
-
(2005)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005), LNCS
, vol.3659
, pp. 427-440
-
-
Good, T.1
Benaissa, M.2
-
21
-
-
51049102787
-
Ultra high performance ECC over NIST primes on commercial FPGAs
-
E. Oswald and P. Rohatgi (Eds.), Berlin: Springer
-
Güneysu T., Paar C.: Ultra high performance ECC over NIST primes on commercial FPGAs. In: Oswald, E., Rohatgi, P. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2008). LNCS, vol. 5154., pp. 62-78. Springer, Berlin (2008).
-
(2008)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2008). LNCS
, vol.5154
, pp. 62-78
-
-
Güneysu, T.1
Paar, C.2
-
24
-
-
84887213050
-
-
Helion Technology: High Performance AES (Rijndael) Cores for Xilinx FPGAs
-
Helion Technology: High Performance AES (Rijndael) Cores for Xilinx FPGAs (2007). http://www. heliontech. com/downloads/aes_xilinx_helioncore. pdf.
-
(2007)
-
-
-
26
-
-
0005498910
-
Hardware evaluation of the AES finalists
-
Ichikawa, T., Kasuya, T., Matsui, M.: Hardware evaluation of the AES finalists. AES Candidate Conference, pp. 13-14 (2000).
-
(2000)
AES Candidate Conference
, pp. 13-14
-
-
Ichikawa, T.1
Kasuya, T.2
Matsui, M.3
-
28
-
-
0037673240
-
A Fully Pipelined Memoryless 17.8 Gbps AES-128 Encryptor
-
ACM Press, New York
-
Järvinen, K. U., Tommiska, M. T., Skyttä, J. O.: A Fully Pipelined Memoryless 17. 8 Gbps AES-128 Encryptor. In: Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA 2003), pp. 207-215. ACM Press, New York (2003).
-
(2003)
Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA 2003)
, pp. 207-215
-
-
Järvinen, K.U.1
Tommiska, M.T.2
Skyttä, J.O.3
-
29
-
-
0001464763
-
Multiplication of multidigit numbers on automata
-
Karatsuba A., Ofman Y.: Multiplication of multidigit numbers on automata. Sov. Phys.-Doklady 7(7), 595-596 (1963).
-
(1963)
Sov. Phys.-Doklady
, vol.7
, Issue.7
, pp. 595-596
-
-
Karatsuba, A.1
Ofman, Y.2
-
30
-
-
84856897095
-
An FPGA Elliptic Curve Cryptographic accelerator over GF(p)
-
McIvor, C., McLoone, M., McCanny, J.: An FPGA Elliptic Curve Cryptographic accelerator over GF(p). In: Irish Signals and Systems Conference (ISSC), pp. 589-594 (2004).
-
(2004)
Irish Signals and Systems Conference (ISSC)
, pp. 589-594
-
-
McIvor, C.1
McLoone, M.2
McCanny, J.3
-
31
-
-
84944878412
-
High performance single-chip FPGA Rijndael algorithm implementations
-
Ç. K. Koç, D. Naccache, and C. Paar (Eds.), Berlin: Springer
-
McLoone M., McCanny J.: High performance single-chip FPGA Rijndael algorithm implementations. In: Koç, Ç. K., Naccache, D., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS, vol. 2162, pp. 65-76. Springer, Berlin (2001).
-
(2001)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS
, vol.2162
, pp. 65-76
-
-
McLoone, M.1
McCanny, J.2
-
32
-
-
0037677855
-
Rijndael FPGA implementations utilising look-up tables
-
McLoone M., McCanny J.: Rijndael FPGA implementations utilising look-up tables. J. VLSI Signal Process. 34(3), 261-275 (2003).
-
(2003)
J. VLSI Signal Process.
, vol.34
, Issue.3
, pp. 261-275
-
-
McLoone, M.1
McCanny, J.2
-
33
-
-
84887213470
-
-
National Institute of Standards and Technology (NIST): Recommended Elliptic Curves for Federal Government Use, July
-
National Institute of Standards and Technology (NIST): Recommended Elliptic Curves for Federal Government Use, July 1999.
-
(1999)
-
-
-
34
-
-
84887213986
-
-
National Institute of Standards and Technology (NIST): FIPS PUB 197: Advanced Encryption Standard
-
National Institute of Standards and Technology (NIST): FIPS PUB 197: Advanced Encryption Standard (2001).
-
(2001)
-
-
-
35
-
-
84887213659
-
-
National Institute of Standards and Technology (NIST): Digital Signature Standard (DSS) (FIPS 186-3), June
-
National Institute of Standards and Technology (NIST): Digital Signature Standard (DSS) (FIPS 186-3), June 2009.
-
(2009)
-
-
-
36
-
-
85099426424
-
m)
-
Ç. K. Koç and C. Paar (Eds.), Berlin: Springer
-
m). In: Koç, Ç. K., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2000). LNCS, vol. 1965, pp. 41-56. Springer, Berlin (2000).
-
(2000)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2000). LNCS
, vol.1965
, pp. 41-56
-
-
Orlando, G.1
Paar, C.2
-
37
-
-
33947673205
-
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
-
Ç. K. Koç, D. Naccache, and C. Paar (Eds.), Berlin: Springer
-
Orlando G., Paar C.: A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware. In: Koç, Ç. K., Naccache, D., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS, vol. 2162., pp. 356-371. Springer, Berlin (2001).
-
(2001)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS
, vol.2162
, pp. 356-371
-
-
Orlando, G.1
Paar, C.2
-
38
-
-
3042688575
-
Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications
-
Rouvroy, G., Standaert, F.-X., Quisquater, J.-J., Legat, J.-D.: Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In: International Conference on Information Technology: Coding and Computing, vol. 2, p. 583 (2004).
-
(2004)
International Conference on Information Technology: Coding and Computing
, vol.2
, pp. 583
-
-
Rouvroy, G.1
Standaert, F.-X.2
Quisquater, J.-J.3
Legat, J.-D.4
-
39
-
-
0038300434
-
A scalable dual-field Elliptic Curve cryptographic processor
-
Satoh A., Takano K.: A scalable dual-field Elliptic Curve cryptographic processor. IEEE Trans. Comput. 52(4), 449-460 (2003).
-
(2003)
IEEE Trans. Comput.
, vol.52
, Issue.4
, pp. 449-460
-
-
Satoh, A.1
Takano, K.2
-
40
-
-
0012584245
-
-
Technical report National Security Agency (NSA), September Available at
-
Solinas, J. A.: Generalized mersenne numbers. Technical report, National Security Agency (NSA), September 1999. Available at http://citeseerx. ist. psu. edu/viewdoc/download?doi=10. 1. 1. 46. 2133& rep=rep1& type=pdf.
-
(1999)
Generalized mersenne numbers
-
-
Solinas, J.A.1
-
41
-
-
35248847435
-
Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements and design tradeoffs
-
C. D. Walter, Ç. K. Koç, and C. Paar (Eds.), Berlin: Springer
-
Standaert F.-X., Rouvroy G., Quisquater J.-J., Legat J.-D.: Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements and design tradeoffs. In: Walter, C. D., Koç, Ç. K., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003). LNCS, vol. 2779, pp. 334-350. Springer, Berlin (2003).
-
(2003)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003). LNCS
, vol.2779
, pp. 334-350
-
-
Standaert, F.-X.1
Rouvroy, G.2
Quisquater, J.-J.3
Legat, J.-D.4
-
42
-
-
38049086644
-
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
-
P. Paillier and I. Verbauwhede (Eds.), Berlin: Springer
-
Suzuki D.: How to Maximize the Potential of FPGA Resources for Modular Exponentiation. In: Paillier, P., Verbauwhede, I. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), LNCS, vol. 4727, pp. 272-288. Springer, Berlin (2007).
-
(2007)
Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), LNCS
, vol.4727
, pp. 272-288
-
-
Suzuki, D.1
-
43
-
-
84887212998
-
-
Xilinx Inc: UG190: Virtex-5 User Guide Available at
-
Xilinx Inc: UG190: Virtex-5 User Guide (2006). Available at http://www. xilinx. com/support/documentation/user_guides/ug190. pdf.
-
(2006)
-
-
-
44
-
-
84887213716
-
-
Xilinx Inc: Xilinx' History of FPGA Development Available at
-
Xilinx Inc: Xilinx' History of FPGA Development (2008). Available at http://www. xilinx. com/company/history. htm.
-
(2008)
-
-
-
45
-
-
84887213405
-
-
Xilinx Inc: Xilinx Spartan-3 and Virtex FPGA devices Available at
-
Xilinx Inc: Xilinx Spartan-3 and Virtex FPGA devices (2008). Available at http://www. xilinx. com/products/silicon_solutions/.
-
(2008)
-
-
|