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Volumn 2162, Issue , 2001, Pages 65-76

High performance single-chip fpga rijndael algorithm implementations

Author keywords

AES; Encryption; FPGA implementation; Rijndael

Indexed keywords

DATA PRIVACY; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN;

EID: 84944878412     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44709-1_7     Document Type: Conference Paper
Times cited : (87)

References (11)
  • 4
    • 0004502409 scopus 로고    scopus 로고
    • Comparison of the Hardware Performance of the AES Candidates using Reconfigurable Hardware
    • 13-14 April, New York, USA
    • K. Gaj, P. Chodowiec: Comparison of the Hardware Performance of the AES Candidates using Reconfigurable Hardware: The Third Advanced Encryption Standard (AES3) Candidate Conference, 13-14 April 2000, New York, USA.
    • (2000) The Third Advanced Encryption Standard (AES3) Candidate Conference
    • Gaj, K.1    Chodowiec, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.