Designing and optimizing compute kernels on NVIDIA GPUs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 224-229

  Jamsek, Damir A ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTE MODELS; MULTI THREADS; PERFORMANCE TUNING; PROGRAMMING MODELS;

DIGITAL INTEGRATED CIRCUITS;

COMPUTER AIDED DESIGN;

EID: 64549110240     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796484     Document Type: Conference Paper

References (3)

1. D. Jamsek "Programming Massively Parallel Processors: The NVIDIA Experience," 45th Design Automation Conference, June 2008.
2. NVIDIA CUDA programming guide. http://www.nvidia.com/cuda
3. S.R. Nassif, Power Grid Analysis benchmarks. In "Proc. IEEE/ACM AS- PDAC," pages 376-381, 2008