Operating principle and integration of in-plane gate logic devices

Applied Physics Letters

Volumn 99, Issue 24, 2011, Pages

  Komatsuzaki, Y ^a   Saba, K ^a   Onomitsu, K ^b   Yamaguchi, H ^b   Horikoshi, Y ^a  

^a WASEDA UNIVERSITY   (Japan)

^b NTT Basic Research Laboratories   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TRANSISTORS; ELECTRICAL CHARACTERISTIC; GATE STRUCTURE; IN-PLANE GATES; INPUT-OUTPUT CHARACTERISTICS; LOAD RESISTANCES; LOGIC OPERATIONS; LOW CURRENTS; OPERATING PRINCIPLES; VOLTAGE TRANSFER CURVES;

PHYSICAL PROPERTIES; PHYSICS;

LOGIC DEVICES;

EID: 83755184037     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3670352     Document Type: Article

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