Adaptive and speculative slack simulations of CMPs on CMPs

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 523-534

  Chen, Jianwei ^a   Dabbiru, Lashkmi Kumar ^a   Wong, Daniel ^a   Annavaram, Murali ^a   Dubois, Michel ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE COHERENCE PROTOCOLS; CHECKPOINT AND ROLLBACK; CHIP MULTIPROCESSOR; CURRENT TRENDS; CYCLE SIMULATION; DIFFERENT ORDER; EXECUTION SPEED; MICRO ARCHITECTURES; PARALLEL PROGRAM; PARALLEL SIMULATIONS; SIMULATION ACCURACY; SIMULATION PLATFORM; TARGET SYSTEMS; VIOLATION RATES;

COMPUTER SIMULATION;

PARALLEL ARCHITECTURES;

EID: 79951711577     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.47     Document Type: Conference Paper

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