CNoC: High-radix clos network-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 12, 2011, Pages 1897-1910

  Kao, Yu Hsiang ^a   Yang, Ming ^a   Artan, N Sertac ^a   Chao, H Jonathan ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

Author keywords

Chip multiprocessor; clos network; high radix NoC; network on chip

Indexed keywords

BUFFER STRUCTURES; CHIP MULTIPROCESSOR; CLOS NETWORK; FLOOR-PLANNING; HIGH THROUGHPUT; HIGH-RADIX NOC; HIGH-SPEED; HOP COUNT; LOAD-BALANCING; NETWORK ON CHIP; PACKET MODE; PROCESSING ELEMENTS; ROUND ROBIN; ROUND-ROBIN MATCHING; ROUTER ARCHITECTURE; TRAFFIC PATTERN; UNIFORM TRAFFIC; VIRTUAL CHANNELS; VIRTUAL OUTPUT QUEUE;

ASYNCHRONOUS SEQUENTIAL LOGIC; BENCHMARKING; COMPUTER ARCHITECTURE; ENERGY EFFICIENCY; NETWORK ARCHITECTURE; NETWORK PERFORMANCE; SCHEDULING ALGORITHMS; SERVERS; THROUGHPUT; TOPOLOGY; VLSI CIRCUITS;

ROUTERS;

EID: 82155192300     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2164538     Document Type: Article

References (34)

1. C. Clos, "A study of non-blocking switching networks," Bell Syst. Tech. J., vol. 32, pp. 406-424, Mar. 1953.
2. D. Pamunuwa, J. Oberg, L. R. Zheng, M. Millberg, A. Jantsch, and H. Tenhunen, "Layout, performance and power trade-offs in mesh-based network-on-chip architectures," in Proc. IFIP Int. Conf. Very Large Scale Integr., Dec. 2003, p. 362.
3. S. R. Ohring, M. Ibel, S. K. Das, and M. J. Kumar, "On generalized fat trees," in Proc. 9th Int. Symp. Parallel Process., Apr. 1995, pp. 37-44.
4. J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP on-chip networks," in Proc. 20th Annu. ICS, 2006, pp. 187-198. (Pubitemid 47168505)
5. J. Kim, J. Balfour, and W. J. Dally, "Flattened butterfly topology for onchip networks," IEEE Comput. Architect. Lett., vol. 6, no. 2, pp. 37-40, Jul.-Dec. 2007.
6. D. Ludovici, F. Gilabert, S. Medardoni, C. Gomez, M. E. Gomez, P. Lopez, G. N. Gaydadjiev, and D. Bertozzi, "Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints," in Proc. Conf. Design, Automat. Test Europe, Apr. 2009, pp. 562-565.
7. A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino, "SPIN: A scalable, packet switched, on-chip micro-network," in Proc. Design Automat. Test Europe Conf. Exhib., Mar. 2003, pp. 70-73.
8. C. Gómez, F. Gilabert, M. E. Gómez, P. Lopez, and J. Duato, "RUFT: Simplifying the fat-tree topology," in Proc. 14th IEEE Int. Conf. Parallel Distrib. Syst., Dec. 2008, pp. 153-160.
9. D. N. Jayasimha, B. Zafar, and Y. Hoskote, "On-chip interconnection networks: Why they are different and how to compare them," Intel Corporation, Santa Clara, CA, Tech. Rep., 2006.
10. T. T. Ye and G. De Micheli, "Physical planning for multiprocessor networks and switch fabrics," in Proc. ASAP, Jun. 2003, pp. 97-107.
11. H. Wang, X. Zhu, L. S. Peh, and S. Malik, "Orion: A power-performance simulator for interconnection networks," in Proc. 35th Int. Symp. Microarchitect., 2002, pp. 294-305.
12. E. Baydal, P. Lopez, and J. Duato, "A family of mechanisms for congestion control in wormhole networks," IEEE Trans. Parallel Distribut. Syst., vol. 16, no. 9, pp. 772-784, Sep. 2005. (Pubitemid 41387759)
13. W. J. Dally, "Wire-efficient VLSI multiprocessor communication networks," in Proc. Stanford Conf. Adv. Res. VLSI, Mar. 1987, pp. 391-415.
14. A. Kumar, P. Kundu, A. Singh, L.-S. Peh, and N. K. Jha, "A 4.6Tbits/s 3.6 GHz single-cycle NoC router with a novel switch allocator in 65 nm CMOS," in Proc. 25th Int. Conf. Comput. Design, Oct. 2007, pp. 63-70.
15. J. Kim, W. J. Dally, B. Towels, and A. K. Gupta, "Microarchitecture of a high-radix router," in Proc. 32th Annu. ISCA, Jun. 2005, pp. 420-431. (Pubitemid 41543459)
16. V. Soteriou, R. S. Ramanujam, B. Lin, and L.-S. Peh, "A high-throughput distributed shared-buffer NoC router," Comput. Architect. Lett., vol. 8, no. 1, pp. 21-24, Jan. 2009.
17. H. J. Chao and J. S. Park, "Centralized contention resolution schemes for a large-capacity optical ATM switch," in Proc. IEEE ATM Workshop, May 1998, pp. 11-16.
18. N. McKeown, "The iSLIP scheduling algorithm for input-queued switches," IEEE/ACM Trans. Netw., vol. 7, no. 2, pp. 188-201, Apr. 1999.
19. H. J. Chao and B. Liu, High Performance Switches and Routers. New York: Wiley-IEEE Press, 2007.
20. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Francisco, CA: Morgan Kaufmann, 2003.
21. Y. Li, S. Panwar, and H. J. Chao, "The dual round-robin matching switch with exustive service," in Proc. HPSR, May 2002, pp. 58-63.
22. P. Gupta and N. McKeown, "Designing and implementing a fast crossbar scheduler," IEEE Micro, vol. 19, no. 1, pp. 20-28, Jan.-Feb. 1999. (Pubitemid 129718403)
23. P. Wijetunga, "High-performance crossbar design for system-on-chip," in Proc. IEEE Int. Workshop Syst.-on-Chip Real-Time Applicat., Jun.-Jul. 2003, pp. 138-143.
24. S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi. (2008). Cacti 5.3 [Online]. Available: http://www.hpl.hp.com/research/cacti
25. M. M. Martin, M. D. Hill, and D. A. Wood, "Token coherence: A new framework for shared-memory multiprocessors," IEEE Micro, vol. 23, no. 6, pp. 108-116, Nov.-Dec. 2003.
26. M. M. K. Martin, "Formal verification and its impact on the snooping versus directory protocol debate," in Proc. IEEE Int. Conf. Comput. Design, Oct. 2005, pp. 543-549. (Pubitemid 44362442)
27. A. Kahng, L. Bin, P. Li-Shiuan, and K. Samadi, "ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration," in Proc. IEEE/ACM Conf. DATE, Apr. 2009, pp. 423-428.
28. J. E. Miller, H. Kasture, G. Kurian, C. Gruenwald, N. Beckmann, C. Celio, J. Eastep, and A. Agarwal, "Graphite: A distributed parallel simulator for multicores," in Proc. Int. Symp. High Performance Comput. Architect., Jan. 2010, pp. 1-12.
29. P. V. Gratz and S. W. Keckler, "Realistic workload characterization and analysis for networks-on-chip design," in Proc. 4th Workshop CMP-MSI, Jan. 2010.
30. M. Lis, K. S. Shim, M. H. Cho, P. Ren, O. Khan, and S. Devadas, "DARSIM: A parallel cycle-level NoC simulator," in Proc. 6th Annu. Workshop Model., Benchmark. Simulat., Jun. 2010.
31. Z. Lu, A. Jantsch, E. Salminen, and C. Grecu, "Network-on-chip benchmarking specification part 2: Microbenchmark specification version 1.0," OCP Int. Partnership Assoc., Inc., Beaverton, OR, Tech. Rep., May 2008.
32. P. Kumar, Y. Pan, J. Kim, G. Memik, and A. Choudhary, "Exploring concentration and channel slicing in on-chip network router," in Proc. Int. Symp. Netw.-on-Chip, May 2009, pp. 276-285.
33. J. Kim, "Low-cost router microarchitecture for on-chip networks," in Proc. Int. Symp. Microarchitect., Dec. 2009, pp. 255-266.
34. T. Krishna, J. Postman, C. Edmonds, L.-S. Peh, and P. Chiang, "SWIFT: A swing-reduced interconnect for a token-based network-on-chip in 90 nm CMOS," in Proc. Int. Conf. Comput. Design, 2010, pp. 439-446.