Flattened butterfly topology for on-chip networks

IEEE Computer Architecture Letters

Volumn 6, Issue 2, 2007, Pages 37-40

  Kim, John ^a   Balfour, James ^a   Dally, William J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Flattened butterfly; High radix routers; On chip networks; Topology

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; NETWORK ROUTING; PROGRAM PROCESSORS;

BYPASS CHANNELS; FLATTENED BUTTERFLY; HIGH RADIX ROUTERS; ON-CHIP NETWORKS;

CHIP SCALE PACKAGES;

EID: 36749031071     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2007.10     Document Type: Article

References (8)

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