Gate circuit layout optimization of power module regarding transient current imbalance

IEEE Transactions on Power Electronics

Volumn 21, Issue 5, 2006, Pages 1176-1183

  Martin, Christian ^b   Guichon, Jean Michel ^c   Schanen, Jean Luc ^a,c   Pasterczyk, Robert J ^a,d  

^a IEEE

^b Univ Claude Bernard Lyon1   (France)

^c LABORATOIRE D ELECTROTECHNIQUE DE GRENOBLE   (France)

^d MGE UPS Systems   (France)

Author keywords

Direct bonding copper (DBC) tracks; Power multichip modules; Printed circuit board (PCB)

Indexed keywords

CIRCUIT THEORY; LOGIC DESIGN; LOGIC GATES; MICROPROCESSOR CHIPS; OPTIMIZATION; PRINTED CIRCUIT BOARDS;

DIRECT BONDING COPPER (DBC) TRACKS; GATE CIRCUIT DISSYMMETRY; POWER MULTICHIP MODULES; TRANSIENT CURRENT IMBALANCE;

INTEGRATED CIRCUIT LAYOUT;

EID: 33947170483     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2006.880356     Document Type: Article

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